Rename ilang to rtlil

frontends/read_ilang/read_ilang.ys → frontends/read_rtlil/read_rtlil.ys

@@ -2,9 +2,9 @@ read_verilog ../top.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang ilang.ilang
+read_rtlil rtlil.il
 dump -n -o file1.il
 
 select -assert-count 1 t:$and

frontends/read_ilang/read_ilang_fsm.ys → frontends/read_rtlil/read_rtlil_fsm.ys

@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang ilang.ilang
+read_rtlil rtlil.il
 dump -n -o file1.il
 stat
 select -assert-count 1 t:$add

frontends/read_ilang/read_ilang_lib.ys → frontends/read_rtlil/read_rtlil_lib.ys

@@ -2,7 +2,7 @@ read_verilog ../top.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang -lib ilang.ilang
+read_rtlil -lib rtlil.il
 dump -n -o file1.il

frontends/read_ilang/read_ilang_lib_fsm.ys → frontends/read_rtlil/read_rtlil_lib_fsm.ys

@@ -2,7 +2,7 @@ read_verilog ../top_fsm.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang -lib ilang.ilang
+read_rtlil -lib rtlil.il
 dump -n -o file1.il

frontends/read_ilang/read_ilang_lib_tri.ys → frontends/read_rtlil/read_rtlil_lib_tri.ys

@@ -2,8 +2,8 @@ read_verilog ../top_tri.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang -lib ilang.ilang
-read_ilang ilang.ilang
+read_rtlil -lib rtlil.il
+read_rtlil rtlil.il
 dump -n -o file1.il

frontends/read_ilang/read_ilang_mem.ys → frontends/read_rtlil/read_rtlil_mem.ys

@@ -2,9 +2,9 @@ read_verilog ../top_mem.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang ilang.ilang
+read_rtlil rtlil.il
 dump -n -o file1.il
 stat
 select -assert-count 2 t:$dff

frontends/read_ilang/read_ilang_mux.ys → frontends/read_rtlil/read_rtlil_mux.ys

@@ -2,9 +2,9 @@ read_verilog ../top_mux.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang ilang.ilang
+read_rtlil rtlil.il
 dump -n -o file1.il
 stat
 select -assert-count 1 t:$shiftx

frontends/read_ilang/read_ilang_nooverwrite.ys → frontends/read_rtlil/read_rtlil_nooverwrite.ys

@@ -2,9 +2,9 @@ read_verilog ../top.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang -nooverwrite ilang.ilang
+read_rtlil -nooverwrite rtlil.il
 dump -n -o file1.il
 
 select -assert-count 1 t:$and

frontends/read_ilang/read_ilang_nooverwrite_fsm.ys → frontends/read_rtlil/read_rtlil_nooverwrite_fsm.ys

@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang -nooverwrite ilang.ilang
+read_rtlil -nooverwrite rtlil.il
 dump -n -o file1.il
 stat
 select -assert-count 1 t:$add

frontends/read_ilang/read_ilang_overwrite.ys → frontends/read_rtlil/read_rtlil_overwrite.ys

@@ -2,9 +2,9 @@ read_verilog ../top.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang -overwrite ilang.ilang
+read_rtlil -overwrite rtlil.il
 dump -n -o file1.il
 
 select -assert-count 1 t:$and

frontends/read_ilang/read_ilang_overwrite_fsm.ys → frontends/read_rtlil/read_rtlil_overwrite_fsm.ys

@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang -overwrite ilang.ilang
+read_rtlil -overwrite rtlil.il
 dump -n -o file1.il
 stat
 select -assert-count 1 t:$add

frontends/read_ilang/read_ilang_parse_error.ys → frontends/read_rtlil/read_rtlil_parse_error.ys

 logger -expect error "Parser error in line 110" 1
-read_ilang ../ilang.ilang
+read_rtlil ../error.il

frontends/read_ilang/read_ilang_selected.ys → frontends/read_rtlil/read_rtlil_selected.ys

@@ -2,9 +2,9 @@ read_verilog ../top.v
 proc
 memory
 dump -o file.il
-write_ilang -selected ilang.ilang
+write_rtlil -selected rtlil.il
 design -reset
-read_ilang ilang.ilang
+read_rtlil rtlil.il
 dump -n -o file1.il
 
 select -assert-count 1 t:$and

frontends/read_ilang/read_ilang_selected_fsm.ys → frontends/read_rtlil/read_rtlil_selected_fsm.ys

@@ -2,9 +2,9 @@ read_verilog ../top_fsm.v
 proc
 memory
 dump -o file.il
-write_ilang -selected  ilang.ilang
+write_rtlil -selected  rtlil.il
 design -reset
-read_ilang ilang.ilang
+read_rtlil rtlil.il
 dump -n -o file1.il
 stat
 select -assert-count 1 t:$add

frontends/read_ilang/read_ilang_tri.ys → frontends/read_rtlil/read_rtlil_tri.ys

@@ -2,9 +2,9 @@ read_verilog ../top_tri.v
 proc
 memory
 dump -o file.il
-write_ilang ilang.ilang
+write_rtlil rtlil.il
 design -reset
-read_ilang ilang.ilang
+read_rtlil rtlil.il
 dump -n -o file1.il
 stat
 select -assert-count 2 t:$mux