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lvzhengyang
yosys-tests
Commits
81d44f17
Commit
81d44f17
authored
May 03, 2019
by
Miodrag Milanovic
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fixes few more
parent
53ae713b
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simple/common.v
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simple/common.v
View file @
81d44f17
module
assert_dff
(
input
clk
,
input
test
,
input
pat
)
;
always
@
(
posedge
clk
)
begin
#
1
;
if
(
test
!=
pat
)
begin
$
display
(
"ERROR: ASSERTION FAILED in %m:"
,
$
time
)
;
...
...
@@ -24,7 +25,7 @@ endmodule
module
assert_Z
(
input
clk
,
input
A
)
;
always
@
(
posedge
clk
)
begin
//
#1;
#
1
;
if
(
A
===
1
'
bZ
)
begin
$
display
(
"ERROR: ASSERTION FAILED in %m:"
,
$
time
,
" "
,
A
)
;
...
...
@@ -36,7 +37,7 @@ endmodule
module
assert_X
(
input
clk
,
input
A
)
;
always
@
(
posedge
clk
)
begin
//
#1;
#
1
;
if
(
A
===
1
'
bX
)
begin
$
display
(
"ERROR: ASSERTION FAILED in %m:"
,
$
time
,
" "
,
A
)
;
...
...
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