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yosys-tests
Commit 8181b44c by SergeyDegtyar
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Review frontends group. 

- read;
- read_aiger;
- read_blif;
- read_ilang;
- read_json.
parent c0b775eb
Showing with 739 additions and 0 deletions
frontends_reviewed/.gitignore 0 → 100644
*/work_*/
/.stamp
/run-test.mk
frontends_reviewed/Makefile 0 → 100644
PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
all::
run-test.mk: ../generate.py
@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
include run-test.mk
.PHONY: all clean
frontends_reviewed/read/read_define.ys 0 → 100644
read -formal ../top.v
read -define MACRO
frontends_reviewed/read/read_define_value.ys 0 → 100644
read -formal ../top.v
read -define MACRO=1
frontends_reviewed/read/read_incdir.ys 0 → 100644
read -formal ../top.v
read -incdir ../include_dir
frontends_reviewed/read/read_undef.ys 0 → 100644
read -formal ../top.v
read -define MACRO
read -undef MACRO
frontends_reviewed/read/read_vhdl.disable 0 → 100644
read -vhdl ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends_reviewed/read/read_vhdl2k.disable 0 → 100644
read -vhdl2k ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends_reviewed/read/read_vhdl87.disable 0 → 100644
read -vhdl87 ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends_reviewed/read/read_vhdl93.disable 0 → 100644
read -vhdl93 ../top.vhd
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
frontends_reviewed/read/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
input clk,
output A,
output cout
);
assign A = y + cin;
assign cout = x + A;
endmodule
frontends_reviewed/read/top.vhd 0 → 100644
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port ( x : in STD_LOGIC;
y : in STD_LOGIC;
cin : in STD_LOGIC;
clk : in STD_LOGIC;
A : out STD_LOGIC;
cout : out STD_LOGIC
);
end entity;
architecture beh of top is
begin
A <= y + cin;
cout <= y + A;
end architecture;
frontends_reviewed/read_aiger/aiger_ff.aig 0 → 100644
aag 7 2 1 2 4
2
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends_reviewed/read_aiger/aiger_ff1.aiger 0 → 100755
aaga 7 2 1 2 4
2
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends_reviewed/read_aiger/aiger_ff2.aiger 0 → 100755
aag 7 2 1 2 4 a
2
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends_reviewed/read_aiger/aiger_ff3.aiger 0 → 100755
aag 7 2 1 2 4
2 s
4
6 8
6
7
8 4 10
10 13 15
12 2 6
14 3 7
frontends_reviewed/read_aiger/aiger_ff4.aiger 0 → 100755
aag 7 2 1 2 4
2
4
6 8
6
7f
8 4 10
10 13 15
12 2 6
14 3 7
frontends_reviewed/read_aiger/aiger_logic.aig 0 → 100644
aag 7 2 0 2 3
2
4
6
12
6 13 15
12 2 4
14 3 5
i0 x
i1 y
o0 s
o1 c
c
half adder
frontends_reviewed/read_aiger/read_aiger.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_aiger aiger.aiger
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_aig.ys 0 → 100644
read_aiger -clk_name clk -module_name top ../aiger_ff.aig
select -assert-count 4 t:$_AND_
select -assert-count 1 t:$_DFF_P_
select -assert-count 4 t:$_NOT_
select -assert-none t:$_AND_ t:$_DFF_P_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_ascii.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_aiger -ascii aiger.aiger
design -reset
read_aiger aiger.aiger
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_bad_state_property_fail.pat 0 → 100644
ERROR: Line 4 cannot be interpreted as a bad state property!
frontends_reviewed/read_aiger/read_aiger_bad_state_property_fail.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch1.aiger
synth -top top
write_verilog synth.v
frontends_reviewed/read_aiger/read_aiger_cant_interpret_as_and_fail.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff4.aiger
synth -top top
write_verilog synth.v
frontends_reviewed/read_aiger/read_aiger_cant_interpret_as_input_fail.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff3.aiger
synth -top top
write_verilog synth.v
frontends_reviewed/read_aiger/read_aiger_cant_interpret_first_char_fail.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger1.aiger
synth -top top
write_verilog synth.v
frontends_reviewed/read_aiger/read_aiger_clk.ys 0 → 100644
read_aiger -clk_name clk ../aiger_ff.aig
select -assert-count 4 t:$_AND_
select -assert-count 1 t:$_DFF_P_
select -assert-count 4 t:$_NOT_
select -assert-none t:$_AND_ t:$_DFF_P_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_clk_module.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_aiger -clk_name clk -module_name top aiger.aiger
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_duplicate_definition_fail.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
synth -top top
write_verilog synth.v
frontends_reviewed/read_aiger/read_aiger_invalid_aiger_header_fail.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff2.aiger
synth -top top
write_verilog synth.v
frontends_reviewed/read_aiger/read_aiger_invalid_reset_literal_fail.pat 0 → 100644
ERROR: Line 1 has invalid reset literal for latch!
frontends_reviewed/read_aiger/read_aiger_invalid_reset_literal_fail.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_latch2.aiger
synth -top top
write_verilog synth.v
frontends_reviewed/read_aiger/read_aiger_latch.ys 0 → 100644
read_aiger -clk_name clk -module_name top ../aiger_latch.aig
stat
select -assert-count 1 t:$_DFF_P_
select -assert-count 1 t:$_NOT_
select -assert-none t:$_DFF_P_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_logic.ys 0 → 100644
read_aiger -clk_name clk -module_name top ../aiger_logic.aig
select -assert-count 3 t:$_AND_
select -assert-count 4 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_map.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_aiger -map aig.map aiger.aiger
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_module.ys 0 → 100644
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_aiger -module_name top aiger.aiger
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_mult.ys 0 → 100644
read_aiger -clk_name clk -module_name top ../aiger_mult.aig
stat
select -assert-count 8 t:$_AND_
select -assert-count 2 t:$dff
select -assert-count 9 t:$_NOT_
select -assert-none t:$_AND_ t:$dff t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_proc.ys 0 → 100644
read_verilog -sv ../top.v
proc
aigmap
write_aiger aiger.aiger
design -reset
read_aiger aiger.aiger
select -assert-count 6 t:$_AND_
select -assert-count 7 t:$_NOT_
select -assert-none t:$_AND_ t:$_NOT_ %% t:* %D
frontends_reviewed/read_aiger/read_aiger_unsup_aiger_file_fail.ys 0 → 100755
read_aiger -clk_name clk -module_name top ../aiger_ff1.aiger
synth -top top
write_verilog synth.v
frontends_reviewed/read_aiger/top.v 0 → 100644
module top
(
input x,
input y,
input cin,
input clk,
output A,
output cout
);
assign A = y + cin;
assign cout = y + A;
endmodule
frontends_reviewed/read_blif/blif_e1.blif 0 → 100755
# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
.modell top
.inputs C S[0] S[1]
.outputs Y[0] Y[1] Y[2] Y[3]
.names $false
.names $true
1
.names $undef
.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
.names $false $1\Y[3:0][0]
1 1
.names $false $1\Y[3:0][1]
1 1
.names $false $1\Y[3:0][2]
1 1
.names $false $1\Y[3:0][3]
1 1
.names $procmux$3_Y[0] $0\Y[3:0][0]
1 1
.names $procmux$3_Y[1] $0\Y[3:0][1]
1 1
.names $procmux$3_Y[2] $0\Y[3:0][2]
1 1
.names $procmux$3_Y[3] $0\Y[3:0][3]
1 1
.end
frontends_reviewed/read_blif/blif_seg_fault.blif 0 → 100755
# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
.model top
.inputs C S[0] S[1]
.outputs Y[0] Y[1] Y[2] Y[3]
.names $false
.names $true
1
.names $undef
.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
.names $false $1\Y[3:0][0]
1 1
.names
1 1
.names $false $1\Y[3:0][2]
1 1
.names $false $1\Y[3:0][3]
1 1
.names $procmux$3_Y[0] $0\Y[3:0][0]
1 1
.names $procmux$3_Y[1] $0\Y[3:0][1]
1 1
.names $procmux$3_Y[2] $0\Y[3:0][2]
1 1
.names $procmux$3_Y[3] $0\Y[3:0][3]
1 1
.end
frontends_reviewed/read_blif/eblif.eblif 0 → 100644
.model top
.names a b
.inputs a
.outputs b
.conn a b
.names a b c
11 1
.cname $my_and_gate
.latch a_and_b dff_q re clk 0
.attr src my_design.v:42
.end
frontends_reviewed/read_blif/eblif_seg_fault.eblif 0 → 100755
.model top
.names a b
.inputs a
.outputs b
.conn a b
.names a b c
11 1
.cname $my_and_gate
.latch a_and_b dff_q re clk 0
.attr my_design.v:42
.end
frontends_reviewed/read_blif/read_blif.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_and_or.ys 0 → 100644
read_verilog ../top_and_or.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 1 t:$dff
select -assert-count 11 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_attr.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -attr blif1.blif
design -reset
read_blif blif1.blif
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_attr_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -attr blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_attr_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -attr blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends_reviewed/read_blif/read_blif_buf.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -buf a a a blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_buf_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -buf a a a blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_buf_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -buf a a a blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends_reviewed/read_blif/read_blif_cname.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -cname blif1.blif
design -reset
read_blif blif1.blif
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_cname_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -cname blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_cname_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -cname blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends_reviewed/read_blif/read_blif_conn.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -conn blif1.blif
design -reset
read_blif blif1.blif
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_conn_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -conn blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_conn_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -conn blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends_reviewed/read_blif/read_blif_duplicate_defenition_fail.pat 0 → 100644
ERROR: Duplicate definition of module top in line 3!
frontends_reviewed/read_blif/read_blif_duplicate_defenition_fail.ys 0 → 100755
read_verilog ../top.v
synth -top top
write_blif blif1.blif
read_blif blif1.blif
frontends_reviewed/read_blif/read_blif_eblif.ys 0 → 100644
read_blif -wideports ../eblif.eblif
stat
select -assert-count 1 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_fsm.ys 0 → 100644
read_verilog ../top_fsm.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 17 t:$dff
select -assert-count 58 t:$lut
#select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_logic.ys 0 → 100644
read_verilog ../top_logic.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 4 t:$dff
select -assert-count 6 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends_reviewed/read_blif/read_blif_param.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif -param blif1.blif
design -reset
read_blif blif1.blif
select -assert-count 2 t:$dff
select -assert-count 2 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_param_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif -param blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_param_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif -param blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 58 t:$lut
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D
frontends_reviewed/read_blif/read_blif_pmux.ys 0 → 100644
read_verilog ../top_pmux.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
stat
select -assert-count 4 t:$dff
select -assert-count 4 t:$lut
select -assert-none t:$dff t:$lut %% t:* %D
frontends_reviewed/read_blif/read_blif_sop.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -sop blif1.blif
select -assert-count 2 t:$dff
select -assert-count 2 t:$sop
select -assert-none t:$dff t:$sop %% t:* %D
frontends_reviewed/read_blif/read_blif_sop_mem.ys 0 → 100644
read_verilog ../top_mem.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -sop blif1.blif
stat
select -assert-count 528 t:$dff
select -assert-count 2372 t:$sop
select -assert-none t:$dff t:$sop %% t:* %D
frontends_reviewed/read_blif/read_blif_sop_mux.ys 0 → 100644
read_verilog ../top_mux.v
synth -top top
write_blif blif1.blif
design -reset
read_blif -sop blif1.blif
stat
select -assert-count 58 t:$sop
select -assert-count 1 t:$paramod\mux4\dw?4
#select -assert-none t:$sop t:$paramod\mux4\dw?4 %% t:* %D
frontends_reviewed/read_blif/read_blif_tri.ys 0 → 100644
read_verilog ../top_tri.v
synth -top top
write_blif blif1.blif
design -reset
read_blif blif1.blif
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