Review frontends group.

- read;
- read_aiger;
- read_blif;
- read_ilang;
- read_json.

frontends_reviewed/.gitignore

+*/work_*/
+/.stamp
+/run-test.mk

frontends_reviewed/Makefile

+PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi)
+
+all::
+
+run-test.mk: ../generate.py
+	@$(PYTHON_EXECUTABLE) ../generate.py > run-test.mk
+
+include run-test.mk
+
+.PHONY: all clean

frontends_reviewed/read/read_define.ys

+read -formal ../top.v
+read -define MACRO

frontends_reviewed/read/read_define_value.ys

+read -formal ../top.v
+read -define MACRO=1

frontends_reviewed/read/read_formal.ys

+read -formal ../top.v

frontends_reviewed/read/read_incdir.ys

+read -formal ../top.v
+read -incdir ../include_dir

frontends_reviewed/read/read_noverific.ys

+read -noverific

frontends_reviewed/read/read_sv.ys

+read -sv ../top.v

frontends_reviewed/read/read_sv2005.ys

+read -sv2005 ../top.v

frontends_reviewed/read/read_sv2009.ys

+read -sv2009 ../top.v

frontends_reviewed/read/read_sv2012.ys

+read -sv2012 ../top.v

frontends_reviewed/read/read_undef.ys

+read -formal ../top.v
+read -define MACRO
+read -undef MACRO

frontends_reviewed/read/read_vhdl.disable

+read -vhdl ../top.vhd
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

frontends_reviewed/read/read_vhdl.ys

+read -vhdl ../top.vhd

frontends_reviewed/read/read_vhdl2k.disable

+read -vhdl2k ../top.vhd
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

frontends_reviewed/read/read_vhdl2k.ys

+read -vhdl2k ../top.vhd

frontends_reviewed/read/read_vhdl87.disable

+read -vhdl87 ../top.vhd
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

frontends_reviewed/read/read_vhdl87.ys

+read -vhdl87 ../top.vhd

frontends_reviewed/read/read_vhdl93.disable

+read -vhdl93 ../top.vhd
+design -reset
+read_verilog ../top.v
+synth -top top
+write_verilog synth.v

frontends_reviewed/read/read_vhdl93.ys

+read -vhdl93 ../top.vhd

frontends_reviewed/read/read_vlog2k.ys

+read -vlog2k ../top.v

frontends_reviewed/read/read_vlog95.ys

+read -vlog95 ../top.v

frontends_reviewed/read/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+ input clk,
+
+ output A,
+ output cout
+ );
+
+ assign    A =  y + cin;
+ assign   cout =  x + A;
+
+endmodule

frontends_reviewed/read/top.vhd

+library IEEE;
+    use IEEE.STD_LOGIC_1164.ALL;
+
+entity top is
+	Port (  x : in STD_LOGIC;
+			y : in STD_LOGIC;
+			cin : in STD_LOGIC;
+			clk : in STD_LOGIC;
+			A : out STD_LOGIC;
+			cout : out STD_LOGIC
+		);
+end entity;
+
+architecture beh of top is
+begin
+	A <= y + cin;
+	cout <= y + A;
+end architecture;

frontends_reviewed/read_aiger/aiger_ff.aig

+aag 7 2 1 2 4
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends_reviewed/read_aiger/aiger_ff1.aiger

+aaga 7 2 1 2 4
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends_reviewed/read_aiger/aiger_ff2.aiger

+aag 7 2 1 2 4 a
+2
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends_reviewed/read_aiger/aiger_ff3.aiger

+aag 7 2 1 2 4
+2 s
+4
+6 8
+6
+7
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends_reviewed/read_aiger/aiger_ff4.aiger

+aag 7 2 1 2 4
+2
+4
+6 8
+6
+7f
+8 4 10
+10 13 15
+12 2 6
+14 3 7

frontends_reviewed/read_aiger/aiger_latch.aig

+aag 1 0 1 2 0
+2 3
+2
+3

frontends_reviewed/read_aiger/aiger_latch1.aiger

+aag 1 0 1 2 0 2
+2 3
+2
+3

frontends_reviewed/read_aiger/aiger_latch2.aiger

+aag 1 0 1 2 0
+2 3 3
+2
+3

frontends_reviewed/read_aiger/aiger_latch3.aiger

+aag 1 0 1 2 0
+2 3
+21
+3

frontends_reviewed/read_aiger/aiger_logic.aig

+aag 7 2 0 2 3
+2
+4
+6
+12
+6 13 15
+12 2 4
+14 3 5
+i0 x
+i1 y
+o0 s
+o1 c
+c
+half adder

frontends_reviewed/read_aiger/read_aiger.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger aiger.aiger
+design -reset
+read_aiger aiger.aiger
+
+select -assert-count 6 t:$_AND_
+select -assert-count 7 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_aig.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff.aig
+
+select -assert-count 4 t:$_AND_
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 4 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_DFF_P_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_ascii.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger -ascii aiger.aiger
+design -reset
+read_aiger aiger.aiger
+
+select -assert-count 6 t:$_AND_
+select -assert-count 7 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_bad_state_property_fail.pat

+ERROR: Line 4 cannot be interpreted as a bad state property!

frontends_reviewed/read_aiger/read_aiger_bad_state_property_fail.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch1.aiger
+
+synth -top top
+write_verilog synth.v

frontends_reviewed/read_aiger/read_aiger_cant_interpret_as_and_fail.pat

+ERROR: Line 6 cannot be interpreted as an AND!

frontends_reviewed/read_aiger/read_aiger_cant_interpret_as_and_fail.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff4.aiger
+
+synth -top top
+write_verilog synth.v

frontends_reviewed/read_aiger/read_aiger_cant_interpret_as_input_fail.pat

+ERROR: Line 2 cannot be interpreted as an input!

frontends_reviewed/read_aiger/read_aiger_cant_interpret_as_input_fail.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff3.aiger
+
+synth -top top
+write_verilog synth.v

frontends_reviewed/read_aiger/read_aiger_cant_interpret_first_char_fail.ys

+read_aiger -clk_name clk -module_name top ../aiger1.aiger
+synth -top top
+write_verilog synth.v

frontends_reviewed/read_aiger/read_aiger_clk.ys

+read_aiger -clk_name clk ../aiger_ff.aig
+
+select -assert-count 4 t:$_AND_
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 4 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_DFF_P_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_clk_module.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger aiger.aiger
+design -reset
+read_aiger -clk_name clk -module_name top aiger.aiger
+
+select -assert-count 6 t:$_AND_
+select -assert-count 7 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_duplicate_definition_fail.pat

+ERROR: Duplicate definition of module top!

frontends_reviewed/read_aiger/read_aiger_duplicate_definition_fail.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
+read_aiger -clk_name clk -module_name top ../aiger_latch3.aiger
+synth -top top
+write_verilog synth.v

frontends_reviewed/read_aiger/read_aiger_invalid_aiger_header_fail.pat

+ERROR: Invalid AIGER header

frontends_reviewed/read_aiger/read_aiger_invalid_aiger_header_fail.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff2.aiger
+
+synth -top top
+write_verilog synth.v

frontends_reviewed/read_aiger/read_aiger_invalid_reset_literal_fail.pat

+ERROR: Line 1 has invalid reset literal for latch!

frontends_reviewed/read_aiger/read_aiger_invalid_reset_literal_fail.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch2.aiger
+
+synth -top top
+write_verilog synth.v

frontends_reviewed/read_aiger/read_aiger_latch.ys

+read_aiger -clk_name clk -module_name top ../aiger_latch.aig
+stat
+select -assert-count 1 t:$_DFF_P_
+select -assert-count 1 t:$_NOT_
+
+select -assert-none t:$_DFF_P_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_logic.ys

+read_aiger -clk_name clk -module_name top ../aiger_logic.aig
+
+select -assert-count 3 t:$_AND_
+select -assert-count 4 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_map.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger aiger.aiger
+design -reset
+read_aiger -map aig.map aiger.aiger
+
+select -assert-count 6 t:$_AND_
+select -assert-count 7 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_module.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger aiger.aiger
+design -reset
+read_aiger -module_name top aiger.aiger
+
+select -assert-count 6 t:$_AND_
+select -assert-count 7 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_mult.ys

+read_aiger -clk_name clk -module_name top ../aiger_mult.aig
+stat
+select -assert-count 8 t:$_AND_
+select -assert-count 2 t:$dff
+select -assert-count 9 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$dff t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_proc.ys

+read_verilog -sv ../top.v
+proc
+aigmap
+write_aiger aiger.aiger
+design -reset
+read_aiger aiger.aiger
+
+select -assert-count 6 t:$_AND_
+select -assert-count 7 t:$_NOT_
+
+select -assert-none t:$_AND_ t:$_NOT_  %% t:* %D

frontends_reviewed/read_aiger/read_aiger_unsup_aiger_file_fail.pat

+ERROR: Unsupported AIGER file!

frontends_reviewed/read_aiger/read_aiger_unsup_aiger_file_fail.ys

+read_aiger -clk_name clk -module_name top ../aiger_ff1.aiger
+
+synth -top top
+write_verilog synth.v

frontends_reviewed/read_aiger/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+ input clk,
+
+ output A,
+ output cout
+ );
+
+ assign    A =  y + cin;
+ assign   cout =  y + A;
+
+endmodule

frontends_reviewed/read_blif/blif_e1.blif

+# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+
+.modell top
+.inputs C S[0] S[1]
+.outputs Y[0] Y[1] Y[2] Y[3]
+.names $false
+.names $true
+1
+.names $undef
+.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
+.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
+.names $false $1\Y[3:0][0]
+1 1
+.names $false $1\Y[3:0][1]
+1 1
+.names $false $1\Y[3:0][2]
+1 1
+.names $false $1\Y[3:0][3]
+1 1
+.names $procmux$3_Y[0] $0\Y[3:0][0]
+1 1
+.names $procmux$3_Y[1] $0\Y[3:0][1]
+1 1
+.names $procmux$3_Y[2] $0\Y[3:0][2]
+1 1
+.names $procmux$3_Y[3] $0\Y[3:0][3]
+1 1
+.end

frontends_reviewed/read_blif/blif_seg_fault.blif

+# Generated by Yosys 0.8+576 (git sha1 0067dc44, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+
+.model top
+.inputs C S[0] S[1]
+.outputs Y[0] Y[1] Y[2] Y[3]
+.names $false
+.names $true
+1
+.names $undef
+.subckt $dff CLK=C D[0]=$procmux$3_Y[0] D[1]=$procmux$3_Y[1] D[2]=$procmux$3_Y[2] D[3]=$procmux$3_Y[3] Q[0]=Y[0] Q[1]=Y[1] Q[2]=Y[2] Q[3]=Y[3]
+.subckt $pmux A[0]=$undef A[1]=$undef A[2]=$undef A[3]=$undef B[0]=$false B[1]=$false B[2]=$false B[3]=$true B[4]=$false B[5]=$false B[6]=$true B[7]=$false B[8]=$false B[9]=$true B[10]=$false B[11]=$false B[12]=$true B[13]=$false B[14]=$false B[15]=$false S[0]=$procmux$4_CMP S[1]=$procmux$5_CMP S[2]=$procmux$6_CMP S[3]=$procmux$7_CMP Y[0]=$procmux$3_Y[0] Y[1]=$procmux$3_Y[1] Y[2]=$procmux$3_Y[2] Y[3]=$procmux$3_Y[3]
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$true Y=$procmux$4_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$true Y=$procmux$5_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$true B[1]=$false Y=$procmux$6_CMP
+.subckt $eq A[0]=S[0] A[1]=S[1] B[0]=$false B[1]=$false Y=$procmux$7_CMP
+.names $false $1\Y[3:0][0]
+1 1
+.names
+1 1
+.names $false $1\Y[3:0][2]
+1 1
+.names $false $1\Y[3:0][3]
+1 1
+.names $procmux$3_Y[0] $0\Y[3:0][0]
+1 1
+.names $procmux$3_Y[1] $0\Y[3:0][1]
+1 1
+.names $procmux$3_Y[2] $0\Y[3:0][2]
+1 1
+.names $procmux$3_Y[3] $0\Y[3:0][3]
+1 1
+.end

frontends_reviewed/read_blif/eblif.eblif

+
+.model top
+.names a b
+.inputs a
+.outputs b
+.conn a b
+.names a b c
+11 1
+.cname $my_and_gate
+.latch a_and_b dff_q re clk 0
+.attr src my_design.v:42
+.end

frontends_reviewed/read_blif/eblif_seg_fault.eblif

+
+.model top
+.names a b
+.inputs a
+.outputs b
+.conn a b
+.names a b c
+11 1
+.cname $my_and_gate
+.latch a_and_b dff_q re clk 0
+.attr my_design.v:42
+.end

frontends_reviewed/read_blif/read_blif.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif
+
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_and_or.ys

+read_verilog ../top_and_or.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 1 t:$dff
+select -assert-count 11 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_attr.ys

+read_verilog ../top.v
+synth -top top
+write_blif -attr blif1.blif
+design -reset
+read_blif blif1.blif
+
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_attr_mem.ys

+read_verilog ../top_mem.v
+synth -top top
+write_blif  -attr blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 528 t:$dff
+select -assert-count 2372 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_attr_mux.ys

+read_verilog ../top_mux.v
+synth -top top
+write_blif -attr blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 58 t:$lut
+select -assert-count 1 t:$paramod\mux4\dw?4
+
+#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D

frontends_reviewed/read_blif/read_blif_buf.ys

+read_verilog ../top.v
+synth -top top
+write_blif -buf a a a blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_buf_mem.ys

+read_verilog ../top_mem.v
+synth -top top
+write_blif -buf a a a blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 528 t:$dff
+select -assert-count 2372 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_buf_mux.ys

+read_verilog ../top_mux.v
+synth -top top
+write_blif -buf a a a blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 58 t:$lut
+select -assert-count 1 t:$paramod\mux4\dw?4
+
+#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D

frontends_reviewed/read_blif/read_blif_cname.ys

+read_verilog ../top.v
+synth -top top
+write_blif -cname blif1.blif
+design -reset
+read_blif blif1.blif
+
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_cname_mem.ys

+read_verilog ../top_mem.v
+synth -top top
+write_blif -cname blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 528 t:$dff
+select -assert-count 2372 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_cname_mux.ys

+read_verilog ../top_mux.v
+synth -top top
+write_blif -cname blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 58 t:$lut
+select -assert-count 1 t:$paramod\mux4\dw?4
+
+#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D

frontends_reviewed/read_blif/read_blif_conn.ys

+read_verilog ../top.v
+synth -top top
+write_blif -conn blif1.blif
+design -reset
+read_blif blif1.blif
+
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_conn_mem.ys

+read_verilog ../top_mem.v
+synth -top top
+write_blif -conn blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 528 t:$dff
+select -assert-count 2372 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_conn_mux.ys

+read_verilog ../top_mux.v
+synth -top top
+write_blif -conn blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 58 t:$lut
+select -assert-count 1 t:$paramod\mux4\dw?4
+
+#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D

frontends_reviewed/read_blif/read_blif_duplicate_defenition_fail.pat

+ERROR: Duplicate definition of module top in line 3!

frontends_reviewed/read_blif/read_blif_duplicate_defenition_fail.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+read_blif blif1.blif

frontends_reviewed/read_blif/read_blif_eblif.ys

+read_blif -wideports ../eblif.eblif
+stat
+select -assert-count 1 t:$dff
+select -assert-count 2 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_fsm.ys

+read_verilog ../top_fsm.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 17 t:$dff
+select -assert-count 58 t:$lut
+
+#select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_logic.ys

+read_verilog ../top_logic.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 4 t:$dff
+select -assert-count 6 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_mem.ys

+read_verilog ../top_mem.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 528 t:$dff
+select -assert-count 2372 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_mux.ys

+read_verilog ../top_mux.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 58 t:$lut
+select -assert-count 1 t:$paramod\mux4\dw?4
+
+#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D

frontends_reviewed/read_blif/read_blif_param.ys

+read_verilog ../top.v
+synth -top top
+write_blif -param blif1.blif
+design -reset
+read_blif blif1.blif
+
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_param_mem.ys

+read_verilog ../top_mem.v
+synth -top top
+write_blif -param blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 528 t:$dff
+select -assert-count 2372 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_param_mux.ys

+read_verilog ../top_mux.v
+synth -top top
+write_blif -param blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 58 t:$lut
+select -assert-count 1 t:$paramod\mux4\dw?4
+
+#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D

frontends_reviewed/read_blif/read_blif_pmux.ys

+read_verilog ../top_pmux.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif
+stat
+select -assert-count 4 t:$dff
+select -assert-count 4 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_sop.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif -sop blif1.blif
+
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$sop
+
+select -assert-none t:$dff t:$sop  %% t:* %D

frontends_reviewed/read_blif/read_blif_sop_mem.ys

+read_verilog ../top_mem.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif -sop blif1.blif
+stat
+select -assert-count 528 t:$dff
+select -assert-count 2372 t:$sop
+
+select -assert-none t:$dff t:$sop  %% t:* %D

frontends_reviewed/read_blif/read_blif_sop_mux.ys

+read_verilog ../top_mux.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif -sop blif1.blif
+stat
+select -assert-count 58 t:$sop
+select -assert-count 1 t:$paramod\mux4\dw?4
+
+#select -assert-none t:$sop t:$paramod\mux4\dw?4 %% t:* %D

frontends_reviewed/read_blif/read_blif_syntax_error_fail.pat

+ERROR: Syntax error in line 3!

frontends_reviewed/read_blif/read_blif_syntax_error_fail.ys

+read_blif ../blif_e1.blif

frontends_reviewed/read_blif/read_blif_tri.ys

+read_verilog ../top_tri.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif blif1.blif

frontends_reviewed/read_blif/read_blif_wideports.ys

+read_verilog ../top.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif -wideports blif1.blif
+
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_wideports_mem.ys

+read_verilog ../top_mem.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif  -wideports blif1.blif
+stat
+select -assert-count 528 t:$dff
+select -assert-count 2372 t:$lut
+
+select -assert-none t:$dff t:$lut  %% t:* %D

frontends_reviewed/read_blif/read_blif_wideports_mux.ys

+read_verilog ../top_mux.v
+synth -top top
+write_blif blif1.blif
+design -reset
+read_blif -wideports blif1.blif
+stat
+select -assert-count 58 t:$lut
+select -assert-count 1 t:$paramod\mux4\dw?4
+
+#select -assert-none t:$lut t:$paramod\mux4\dw?4 %% t:* %D

frontends_reviewed/read_blif/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+
+endmodule

frontends_reviewed/read_blif/top_and_or.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+
+ initial begin
+    B = 0;
+ end
+
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+
+endmodule

frontends_reviewed/read_blif/top_fsm.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

frontends_reviewed/read_blif/top_logic.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg A1,cout1;
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A1 <=  ~y + &cin;
+end
+always @(posedge x) begin
+    cout1 <= cin ? |y : ^A;
+end
+
+always @(posedge x) begin
+        A <=  A1|y~&cin~^A1;
+end
+always @(posedge x) begin
+        cout <=  cout1&cin~|y;
+end
+
+endmodule

frontends_reviewed/read_blif/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	parameter WIDTH=8;
+	// Declare the RAM variable
+	reg [WIDTH-1:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clk)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

frontends_reviewed/read_blif/top_mux.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+parameter dw=4;
+
+input[1:0] S;
+input[dw-1:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[dw-1:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 #(4) u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends_reviewed/read_blif/top_pmux.v

+module top(C, S, Y);
+input C;
+input [1:0] S;
+output reg [3:0] Y;
+
+initial Y = 0;
+
+always @(posedge C) begin
+        case (S)
+                2'b00: Y <= 4'b0001;
+                2'b01: Y <= 4'b0010;
+                2'b10: Y <= 4'b0100;
+                2'b11: Y <= 4'b1000;
+        endcase
+end
+
+endmodule

frontends_reviewed/read_blif/top_tri.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;
+    output [1:0] o;
+
+    wire [1:0] io;
+	assign 	io[0] = (en)? i : 1'bZ;
+
+    assign 	io[1] = (i)? en : 1'bZ;
+
+    assign o = io;
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

frontends_reviewed/read_ilang/file.il

+
+autoidx 15
+
+attribute \cells_not_processed 1
+attribute \src "top.v:1"
+module \top
+
+  attribute \src "top.v:17"
+  wire $0\B[0:0]
+
+  attribute \src "top.v:19"
+  attribute \unused_bits "1"
+  wire width 2 $and$top.v:19$4_Y
+
+  attribute \src "top.v:18"
+  wire $logic_and$top.v:18$2_Y
+
+  attribute \src "top.v:20"
+  wire $logic_and$top.v:20$6_Y
+
+  attribute \src "top.v:20"
+  wire $logic_not$top.v:20$5_Y
+
+  attribute \src "top.v:18"
+  wire $logic_or$top.v:18$3_Y
+
+  attribute \src "top.v:20"
+  wire $logic_or$top.v:20$7_Y
+
+  attribute \src "top.v:21"
+  attribute \unused_bits "1"
+  wire width 2 $or$top.v:21$8_Y
+
+  wire $procmux$10_Y
+
+  attribute \src "top.v:8"
+  wire input 5 \A
+
+  attribute \init 1'0
+  attribute \src "top.v:9"
+  wire output 6 \B
+
+  attribute \src "top.v:6"
+  wire input 4 \clk
+
+  attribute \src "top.v:3"
+  wire width 2 input 1 \x
+
+  attribute \src "top.v:4"
+  wire width 2 input 2 \y
+
+  attribute \src "top.v:5"
+  wire width 2 input 3 \z
+
+  attribute \src "top.v:19"
+  cell $and $and$top.v:19$4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \z
+    connect \Y $and$top.v:19$4_Y
+  end
+
+  attribute \src "top.v:18"
+  cell $logic_and $logic_and$top.v:18$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B \z
+    connect \Y $logic_and$top.v:18$2_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_and $logic_and$top.v:20$6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B $logic_not$top.v:20$5_Y
+    connect \Y $logic_and$top.v:20$6_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_not $logic_not$top.v:20$5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \z
+    connect \Y $logic_not$top.v:20$5_Y
+  end
+
+  attribute \src "top.v:18"
+  cell $logic_or $logic_or$top.v:18$3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:18$2_Y
+    connect \Y $logic_or$top.v:18$3_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $logic_or $logic_or$top.v:20$7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:20$6_Y
+    connect \Y $logic_or$top.v:20$7_Y
+  end
+
+  attribute \src "top.v:21"
+  cell $or $or$top.v:21$8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \x
+    connect \Y $or$top.v:21$8_Y
+  end
+
+  attribute \src "top.v:17"
+  cell $dff $procdff$14
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D $0\B[0:0]
+    connect \Q \B
+  end
+
+  attribute \src "top.v:18"
+  cell $mux $procmux$10
+    parameter \WIDTH 1
+    connect \A \B
+    connect \B $and$top.v:19$4_Y [0]
+    connect \S $logic_or$top.v:18$3_Y
+    connect \Y $procmux$10_Y
+  end
+
+  attribute \src "top.v:20"
+  cell $mux $procmux$12
+    parameter \WIDTH 1
+    connect \A $procmux$10_Y
+    connect \B $or$top.v:21$8_Y [0]
+    connect \S $logic_or$top.v:20$7_Y
+    connect \Y $0\B[0:0]
+  end
+end

frontends_reviewed/read_ilang/ilang.ilang

+# Generated by Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)
+autoidx 15
+attribute \cells_not_processed 1
+attribute \src "top.v:1"
+module \top
+  attribute \src "top.v:17"
+  wire $0\B[0:0]
+  attribute \src "top.v:19"
+  attribute \unused_bits "1"
+  wire width 2 $and$top.v:19$4_Y
+  attribute \src "top.v:18"
+  wire $logic_and$top.v:18$2_Y
+  attribute \src "top.v:20"
+  wire $logic_and$top.v:20$6_Y
+  attribute \src "top.v:20"
+  wire $logic_not$top.v:20$5_Y
+  attribute \src "top.v:18"
+  wire $logic_or$top.v:18$3_Y
+  attribute \src "top.v:20"
+  wire $logic_or$top.v:20$7_Y
+  attribute \src "top.v:21"
+  attribute \unused_bits "1"
+  wire width 2 $asdfasdfasfor$top.v:21$8_Y
+  wire $procmux$10_Y
+  attribute \src "top.v:8"
+  wire input 5 \A
+  attribute \init 1'0
+  attribute \src "top.v:9"
+  wire output 6 \B
+  attribute \src "top.v:6"
+  wire input 4 \clk
+  attribute \src "top.v:3"
+  wire width 2 input 1 \x
+  attribute \src "top.v:4"
+  wire width 2 input 2 \y
+  attribute \src "top.v:5"
+  wire width 2 input 3 \z
+  attribute \src "top.v:19"
+  cell $and $and$top.v:19$4
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \z
+    connect \Y $and$top.v:19$4_Y
+  end
+  attribute \src "top.v:18"
+  cell $logic_and $logic_and$top.v:18$2
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B \z
+    connect \Y $logic_and$top.v:18$2_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_and $logic_and$top.v:20$6
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \y
+    connect \B $logic_not$top.v:20$5_Y
+    connect \Y $logic_and$top.v:20$6_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_not $logic_not$top.v:20$5
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \Y_WIDTH 1
+    connect \A \z
+    connect \Y $logic_not$top.v:20$5_Y
+  end
+  attribute \src "top.v:18"
+  cell $logic_or $logic_or$top.v:18$3
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:18$2_Y
+    connect \Y $logic_or$top.v:18$3_Y
+  end
+  attribute \src "top.v:20"
+  cell $logic_or $logic_or$top.v:20$7
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 2
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 1
+    parameter \Y_WIDTH 1
+    connect \A \x
+    connect \B $logic_and$top.v:20$6_Y
+    connect \Y $logic_or$top.v:20$7_Y
+  end
+  attribute \src "top.v:21"
+  cell $or $or$top.v:21$8
+    parameter \A_SIGNED 0
+    parameter \A_WIDTH 1
+    parameter \B_SIGNED 0
+    parameter \B_WIDTH 2
+    parameter \Y_WIDTH 2
+    connect \A \A
+    connect \B \x
+    connect \Y $or$top.v:21$8_Y
+  end
+  attribute \src "top.v:17"
+  cell $dff $procdff$14
+    parameter \CLK_POLARITY 1'1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D $0\B[0:0]
+    connect \Q \B
+  end
+  attribute \src "top.v:18"
+  cell $mux $procmux$10
+    parameter \WIDTH 1
+    connect \A \B
+    connect \B $and$top.v:19$4_Y [0]
+    connect \S $logic_or$top.v:18$3_Y
+    connect \Y $procmux$10_Y
+  end
+  attribute \src "top.v:20"
+  cell $mux $procmux$12
+    parameter \WIDTH 1
+    connect \A $procmux$10_Y
+    connect \B $or$top.v:21$8_Y [0]
+    connect \S $logic_or$top.v:20$7_Y
+    connect \Y $0\B[0:0]
+  end
+end

frontends_reviewed/read_ilang/read_ilang.ys

+read_verilog ../top.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+
+select -assert-count 1 t:$and
+select -assert-count 1 t:$dff
+select -assert-count 2 t:$logic_and
+select -assert-count 1 t:$logic_not
+select -assert-count 2 t:$logic_or
+select -assert-count 2 t:$mux
+select -assert-count 1 t:$or
+
+select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D

frontends_reviewed/read_ilang/read_ilang_fsm.ys

+read_verilog ../top_fsm.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+stat
+select -assert-count 1 t:$add
+select -assert-count 2 t:$dff
+select -assert-count 33 t:$eq
+select -assert-count 2 t:$gt
+select -assert-count 1 t:$logic_and
+select -assert-count 3 t:$logic_or
+select -assert-count 19 t:$mux
+select -assert-count 1 t:$not
+select -assert-count 1 t:$pmux
+
+#select -assert-none t:$add t:$dff t:$eq t:$gt t:$logic_and t:$logic_or t:$mux t:$not t:$pmux %% t:* %D

frontends_reviewed/read_ilang/read_ilang_lib.ys

+read_verilog ../top.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang -lib ilang.ilang
+dump -n -o file1.il

frontends_reviewed/read_ilang/read_ilang_lib_fsm.ys

+read_verilog ../top_fsm.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang -lib ilang.ilang
+dump -n -o file1.il

frontends_reviewed/read_ilang/read_ilang_lib_tri.ys

+read_verilog ../top_tri.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang -lib ilang.ilang
+read_ilang ilang.ilang
+dump -n -o file1.il

frontends_reviewed/read_ilang/read_ilang_mem.ys

+read_verilog ../top_mem.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+stat
+select -assert-count 2 t:$dff
+select -assert-count 1 t:$mem
+select -assert-count 10 t:$mux
+
+select -assert-none t:$dff t:$mem t:$mux %% t:* %D

frontends_reviewed/read_ilang/read_ilang_mux.ys

+read_verilog ../top_mux.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+stat
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$mux
+select -assert-count 12 t:$eq
+select -assert-count 2 t:$pmux

frontends_reviewed/read_ilang/read_ilang_nooverwrite.ys

+read_verilog ../top.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang -nooverwrite ilang.ilang
+dump -n -o file1.il
+
+select -assert-count 1 t:$and
+select -assert-count 1 t:$dff
+select -assert-count 2 t:$logic_and
+select -assert-count 1 t:$logic_not
+select -assert-count 2 t:$logic_or
+select -assert-count 2 t:$mux
+select -assert-count 1 t:$or
+
+select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D

frontends_reviewed/read_ilang/read_ilang_nooverwrite_fsm.ys

+read_verilog ../top_fsm.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang -nooverwrite ilang.ilang
+dump -n -o file1.il
+stat
+select -assert-count 1 t:$add
+select -assert-count 2 t:$dff
+select -assert-count 33 t:$eq
+select -assert-count 2 t:$gt
+select -assert-count 1 t:$logic_and
+select -assert-count 3 t:$logic_or
+select -assert-count 19 t:$mux
+select -assert-count 1 t:$not
+select -assert-count 1 t:$pmux
+
+#select -assert-none t:$add t:$dff t:$eq t:$gt t:$logic_and t:$logic_or t:$mux t:$not t:$pmux %% t:* %D

frontends_reviewed/read_ilang/read_ilang_overwrite.ys

+read_verilog ../top.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang -overwrite ilang.ilang
+dump -n -o file1.il
+
+select -assert-count 1 t:$and
+select -assert-count 1 t:$dff
+select -assert-count 2 t:$logic_and
+select -assert-count 1 t:$logic_not
+select -assert-count 2 t:$logic_or
+select -assert-count 2 t:$mux
+select -assert-count 1 t:$or
+
+select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D

frontends_reviewed/read_ilang/read_ilang_overwrite_fsm.ys

+read_verilog ../top_fsm.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang -overwrite ilang.ilang
+dump -n -o file1.il
+stat
+select -assert-count 1 t:$add
+select -assert-count 2 t:$dff
+select -assert-count 33 t:$eq
+select -assert-count 2 t:$gt
+select -assert-count 1 t:$logic_and
+select -assert-count 3 t:$logic_or
+select -assert-count 19 t:$mux
+select -assert-count 1 t:$not
+select -assert-count 1 t:$pmux
+
+#select -assert-none t:$add t:$dff t:$eq t:$gt t:$logic_and t:$logic_or t:$mux t:$not t:$pmux %% t:* %D

frontends_reviewed/read_ilang/read_ilang_parse_error_fail.pat

+ERROR: Parser error in line 110: ilang error: wire $or$top.v:21$8_Y not found

frontends_reviewed/read_ilang/read_ilang_parse_error_fail.ys

+read_ilang ../ilang.ilang
+dump -n -o file1.il
+write_verilog synth.v

frontends_reviewed/read_ilang/read_ilang_selected.ys

+read_verilog ../top.v
+proc
+memory
+dump -o file.il
+write_ilang -selected ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+
+select -assert-count 1 t:$and
+select -assert-count 1 t:$dff
+select -assert-count 2 t:$logic_and
+select -assert-count 1 t:$logic_not
+select -assert-count 2 t:$logic_or
+select -assert-count 2 t:$mux
+select -assert-count 1 t:$or
+
+select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D

frontends_reviewed/read_ilang/read_ilang_selected_fsm.ys

+read_verilog ../top_fsm.v
+proc
+memory
+dump -o file.il
+write_ilang -selected  ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+stat
+select -assert-count 1 t:$add
+select -assert-count 2 t:$dff
+select -assert-count 33 t:$eq
+select -assert-count 2 t:$gt
+select -assert-count 1 t:$logic_and
+select -assert-count 3 t:$logic_or
+select -assert-count 19 t:$mux
+select -assert-count 1 t:$not
+select -assert-count 1 t:$pmux
+
+#select -assert-none t:$add t:$dff t:$eq t:$gt t:$logic_and t:$logic_or t:$mux t:$not t:$pmux %% t:* %D

frontends_reviewed/read_ilang/read_ilang_tri.ys

+read_verilog ../top_tri.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+design -reset
+read_ilang ilang.ilang
+dump -n -o file1.il
+stat
+select -assert-count 2 t:$mux

frontends_reviewed/read_ilang/top.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+
+ initial begin
+    B = 0;
+ end
+
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+
+endmodule

frontends_reviewed/read_ilang/top_fsm.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

frontends_reviewed/read_ilang/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

frontends_reviewed/read_ilang/top_mux.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends_reviewed/read_ilang/top_tri.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;
+    output [1:0] o;
+
+    wire [1:0] io;
+	assign 	io[0] = (en)? i : 1'bZ;
+
+    assign 	io[1] = (i)? en : 1'bZ;
+
+    assign o = io;
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

frontends_reviewed/read_json/json1.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "directisson": "inpusdfsdft",
+          "bitsss": [ a ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "A": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:8"
+          }
+        },
+        "x": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "y": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        }
+      }
+    }
+  }
+}

frontends_reviewed/read_json/json2.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "directisson": "inpusdfsdft",
+          "bitsss": [ 2 ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "A": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:8"
+          }
+        },
+        "x": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "y": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        }
+      }
+    }
+  }
+}

frontends_reviewed/read_json/json3.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "direction": "input",
+          "bitsss": [ 2 ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "A": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:8"
+          }
+        },
+        "x": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "y": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        }
+      }
+    }
+  }
+}

frontends_reviewed/read_json/json4.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "direction": "insdfasdfput",
+          "bits": [ 2 ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "A": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:8"
+          }
+        },
+        "x": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "y": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        }
+      }
+    }
+  }
+}

frontends_reviewed/read_json/json5.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "A": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:8"
+          }
+        },
+        "x": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "y": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        }
+      }
+    }
+  }
+

frontends_reviewed/read_json/json6.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "A": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hide_name": 0,
+          "bissts": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:8"
+          }
+        },
+        "x": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "y": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        }
+      }
+    }
+  }
+}

frontends_reviewed/read_json/json7.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": 8,
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        "A": {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hisssde_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:8"
+          }
+        },
+        "x": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "y": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        }
+      }
+    }
+  }
+}

frontends_reviewed/read_json/json8.json

+{
+  "creator": "Yosys 0.8+583 (git sha1 030483ff, gcc 8.3.0-6ubuntu1~18.10.1 -Og -fPIC)",
+  "modules": {
+    "top": {
+      "attributes": {
+        "cells_not_processed": 1,
+        "src": "top.v:1"
+      },
+      "ports": {
+        "x": {
+          "direction": "input",
+          "bits": [ 2 ]
+        },
+        "y": {
+          "direction": "input",
+          "bits": [ 3 ]
+        },
+        "cin": {
+          "direction": "input",
+          "bits": [ 4 ]
+        },
+        "A": {
+          "direction": "output",
+          "bits": [ 5 ]
+        },
+        "cout": {
+          "direction": "output",
+          "bits": [ 6 ]
+        }
+      },
+      "cells": {
+        "$add$top.v:18$2": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:18"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 4 ],
+            "Y": [ 7 ]
+          }
+        },
+        "$add$top.v:21$4": {
+          "hide_name": 1,
+          "type": "$add",
+          "parameters": {
+            "A_SIGNED": 0,
+            "A_WIDTH": 1,
+            "B_SIGNED": 0,
+            "B_WIDTH": 1,
+            "Y_WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:21"
+          },
+          "port_directions": {
+            "A": "input",
+            "B": "input",
+            "Y": "output"
+          },
+          "connections": {
+            "A": [ 3 ],
+            "B": [ 5 ],
+            "Y": [ 8 ]
+          }
+        },
+        "$procdff$6": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 0,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:20"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 8 ],
+            "Q": [ 6 ]
+          }
+        },
+        "$procdff$7": {
+          "hide_name": 1,
+          "type": "$dff",
+          "parameters": {
+            "CLK_POLARITY": 1,
+            "WIDTH": 1
+          },
+          "attributes": {
+            "src": "top.v:17"
+          },
+          "port_directions": {
+            "CLK": "input",
+            "D": "input",
+            "Q": "output"
+          },
+          "connections": {
+            "CLK": [ 2 ],
+            "D": [ 7 ],
+            "Q": [ 5 ]
+          }
+        }
+      },
+      "netnames": {
+        "$0\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:17"
+          }
+        },
+        "$0\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:20"
+          }
+        },
+        "$1\\A[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$1\\cout[0:0]": {
+          "hide_name": 1,
+          "bits": [ "0" ],
+          "attributes": {
+            "src": "top.v:11"
+          }
+        },
+        "$add$top.v:18$2_Y": {
+          "hide_name": 1,
+          "bits": [ 7 ],
+          "attributes": {
+            "src": "top.v:18"
+          }
+        },
+        "$add$top.v:21$4_Y": {
+          "hide_name": 1,
+          "bits": [ 8 ],
+          "attributes": {
+            "src": "top.v:21"
+          }
+        },
+        3: {
+          "hide_name": 0,
+          "bits": [ 5 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:7"
+          }
+        },
+        "cin": {
+          "hide_name": 0,
+          "bits": [ 4 ],
+          "attributes": {
+            "src": "top.v:5"
+          }
+        },
+        "cout": {
+          "hide_name": 0,
+          "bits": [ 6 ],
+          "attributes": {
+            "init": 0,
+            "src": "top.v:8"
+          }
+        },
+        "x": {
+          "hide_name": 0,
+          "bits": [ 2 ],
+          "attributes": {
+            "src": "top.v:3"
+          }
+        },
+        "y": {
+          "hide_name": 0,
+          "bits": [ 3 ],
+          "attributes": {
+            "src": "top.v:4"
+          }
+        }
+      }
+    }
+  }
+}

frontends_reviewed/read_json/read_json.ys

+read_verilog ../top.v
+proc
+write_json json.json
+design -reset
+read_json json.json
+
+select -assert-count 2 t:$dff
+select -assert-count 2 t:$add
+
+select -assert-none t:$dff t:$add  %% t:* %D

frontends_reviewed/read_json/read_json_fsm.ys

+read_verilog ../top_fsm.v
+proc
+write_json json.json
+design -reset
+read_json json.json

frontends_reviewed/read_json/read_json_invalid_direction_fail.pat

+ERROR: JSON port node 'x' has invalid 'insdfasdfput' direction attribute.

frontends_reviewed/read_json/read_json_invalid_direction_fail.ys

+read_json ../json4.json

frontends_reviewed/read_json/read_json_logic.ys

+read_verilog ../top_logic.v
+proc
+write_json json.json
+design -reset
+read_json json.json
+
+select -assert-count 1 t:$and
+select -assert-count 1 t:$dff
+select -assert-count 2 t:$logic_and
+select -assert-count 1 t:$logic_not
+select -assert-count 2 t:$logic_or
+select -assert-count 2 t:$mux
+select -assert-count 1 t:$or
+
+select -assert-none t:$and t:$dff t:$logic_and t:$logic_not t:$logic_or t:$mux t:$or %% t:* %D

frontends_reviewed/read_json/read_json_mem.ys

+read_verilog ../top_mem.v
+proc
+memory
+write_json json.json
+design -reset
+read_json json.json
+stat
+select -assert-count 2 t:$dff
+select -assert-count 1 t:$mem
+select -assert-count 10 t:$mux
+
+select -assert-none t:$dff t:$mem t:$mux  %% t:* %D

frontends_reviewed/read_json/read_json_mem_noproc.ys

+read_verilog ../top_mem.v
+write_json json.json
+design -reset
+read_json json.json
+stat
+select -assert-count 2 t:$memrd
+select -assert-count 2 t:$memwr
+
+select -assert-none t:$memrd t:$memwr %% t:* %D

frontends_reviewed/read_json/read_json_mux.ys

+read_verilog ../top_mux.v
+proc
+write_json json.json
+design -reset
+read_json json.json
+stat
+select -assert-count 1 t:$shiftx
+select -assert-count 1 t:$mux
+select -assert-count 12 t:$eq
+select -assert-count 2 t:$pmux

frontends_reviewed/read_json/read_json_no_bits_fail.pat

+ERROR: JSON port node 'x' has no bits attribute.

frontends_reviewed/read_json/read_json_no_bits_fail.ys

+read_json ../json3.json

frontends_reviewed/read_json/read_json_no_direction_fail.pat

+ERROR: JSON port node 'x' has no direction attribute.

frontends_reviewed/read_json/read_json_no_direction_fail.ys

+read_json ../json2.json

frontends_reviewed/read_json/read_json_nonarray_bits_attr_fail.pat

+ERROR: JSON netname node '$add$top.v:21$4_Y' has non-array bits attribute.

frontends_reviewed/read_json/read_json_nonarray_bits_attr_fail.ys

+read_json ../json7.json

frontends_reviewed/read_json/read_json_nonstring_key_fail.pat

+ERROR: Unexpected non-string key in JSON dict.

frontends_reviewed/read_json/read_json_nonstring_key_fail.ys

+read_json ../json8.json

frontends_reviewed/read_json/read_json_tri.ys

+read_verilog ../top_tri.v
+proc
+write_json json.json
+design -reset
+read_json json.json
+stat
+select -assert-count 2 t:$mux

frontends_reviewed/read_json/read_json_unexpected_char_fail.pat

+ERROR: Unexpected character in JSON file: 'a'

frontends_reviewed/read_json/read_json_unexpected_char_fail.ys

+read_json ../json1.json

frontends_reviewed/read_json/read_json_unexpected_eof_fail.pat

+ERROR: Unexpected EOF in JSON file.

frontends_reviewed/read_json/read_json_unexpected_eof_fail.ys

+read_json ../json5.json

frontends_reviewed/read_json/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ initial begin
+    A = 0;
+    cout = 0;
+ end
+
+always @(posedge x) begin
+    A <=  y + cin;
+end
+always @(negedge x) begin
+    cout <=  y + A;
+end
+
+endmodule

frontends_reviewed/read_json/top_fsm.v

+module FSM ( clk,rst, en, ls, rs, stop, busy, finish);
+	input wire clk;
+	input wire rst;
+	input wire en;
+	input wire ls;
+	input wire rs;
+
+	output wire stop;
+	output wire busy;
+	output wire finish;
+	
+    parameter S0 = 4'b0000, S1 = 4'b0001, S2 = 4'b0010, S3 = 4'b0011, S4 = 4'b0100, S5 = 4'b0101, S6 = 4'b0110, S7 = 4'b0111, S8 = 4'b1000, S9 = 4'b1001, S10 = 4'b1010, S11 = 4'b1011, S12 = 4'b1100, S13 = 4'b1101, S14 = 4'b1110;
+	
+	reg [3:0] ns, st;
+
+	reg [2:0] count;
+
+
+	always @(posedge clk)
+	begin : CurrstProc
+		if (rst)
+			st <= S0;
+		else
+			st <= ns;
+	end
+
+	always @*
+	begin : NextstProc
+		ns = st;
+		case (st)
+			S0: ns = S1;
+			S1: ns = S2;
+			S2:
+				if (rs == 1'b1)
+					ns = S3;
+				else
+					ns = S4;
+			S3: ns = S1;
+			S4: if (count > 7)
+					ns = S10;
+				else
+					ns = S5;
+			S5: if (ls == 1'b0)
+					ns = S6;
+				else
+					ns = S3;
+			S6:
+				if (ls == 1'b1)
+					ns = S7;
+				else
+					ns = S8;
+			S7:
+				if (ls == 1'b1 && rs == 1'b1)
+					ns = S5;
+				else
+					ns = S13;
+			S8: ns = S9;
+			S9: ns = S8;
+			S10:
+				if (ls == 1'b1 || rs == 1'b1)
+					ns = S11;
+				else
+					ns = S4;
+			S11: ns = S12;
+			S12: ns = S10;
+			S13: ;
+			default: ns = S0;
+		endcase;
+	end
+	
+	always @(posedge clk)
+		if(~rst)
+			count <= 0;
+		else
+		begin
+			if(st == S4)
+				if (count > 7)
+					count <= 0;
+				else
+					count <= count + 1;
+		end
+
+	//FSM outputs (combinatorial)
+
+	assign stop   = (st == S3 || st == S12) ? 1'b1 : 1'b0;
+
+	assign finish = (st == S13) ? 1'b1 : 1'b0;
+
+	assign busy   = (st == S8 || st == S9) ? 1'b1 : 1'b0;
+
+endmodule
+
+
+module top (
+input clk,
+input rst,
+input en,
+input a,
+input b,
+output s,
+output bs,
+output f
+);
+
+FSM u_FSM ( .clk(clk),
+            .rst(rst), 
+            .en(en), 
+            .ls(a), 
+            .rs(b), 
+            .stop(s), 
+            .busy(bs), 
+            .finish(f));
+
+endmodule

frontends_reviewed/read_json/top_logic.v

+module top
+(
+ input [1:0] x,
+ input [1:0] y,
+ input [1:0] z,
+ input clk,
+
+ input A,
+ output reg B
+ );
+
+ initial begin
+    B = 0;
+ end
+
+always @(posedge clk) begin
+    if (x || y && z)
+        B <=  A & z;
+    if (x || y && !z)
+        B <=  A | x;
+end
+
+endmodule

frontends_reviewed/read_json/top_mem.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	initial begin
+        q_a <= 8'h00;
+        q_b <= 8'd0;
+	end
+
+	// Port A
+	always @ (posedge clka)
+	begin
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+
+	// Port B
+	always @ (posedge clkb)
+	begin
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+
+endmodule

frontends_reviewed/read_json/top_mux.v

+module mux2 (S,A,B,Y);
+    input S;
+    input A,B;
+    output reg Y;
+
+    always @(*)
+		Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+    case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+   endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+   case( S )
+       0 : Y = D[0];
+       1 : Y = D[1];
+       2 : Y = D[2];
+       3 : Y = D[3];
+       4 : Y = D[4];
+       5 : Y = D[5];
+       6 : Y = D[6];
+       7 : Y = D[7];
+   endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ 	input  [15:0] D;
+ 	input  [3:0] S;
+ 	output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+        .S (S[0]),
+        .A (D[0]),
+        .B (D[1]),
+        .Y (M2)
+    );
+
+
+mux4 u_mux4 (
+        .S (S[1:0]),
+        .D (D[3:0]),
+        .Y (M4)
+    );
+
+mux8 u_mux8 (
+        .S (S[2:0]),
+        .D (D[7:0]),
+        .Y (M8)
+    );
+
+mux16 u_mux16 (
+        .S (S[3:0]),
+        .D (D[15:0]),
+        .Y (M16)
+    );
+
+endmodule

frontends_reviewed/read_json/top_tri.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;
+    output [1:0] o;
+
+    wire [1:0] io;
+	assign 	io[0] = (en)? i : 1'bZ;
+
+    assign 	io[1] = (i)? en : 1'bZ;
+
+    assign o = io;
+
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule