Add test15-17

architecture/synth_xilinx_srl/generate.py

@@ -157,7 +157,7 @@ endmodule
 
 # Test 11: neg_clk_with_enable_with_init_inferred_var_len
 for i in range(1,N+1):
-    with open('test1_%d.v' % i, 'w') as fp:
+    with open('test11_%d.v' % i, 'w') as fp:
         fp.write('''
 module test11_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
 generate 
@@ -180,3 +180,49 @@ generate
 endgenerate
 endmodule
 '''.format(i))
+
+# Test 15: pos_clk_no_enable_no_init_not_inferred
+for i in range(128+1,128+N+1):
+    with open('test15_%d.v' % i, 'w') as fp:
+        fp.write('''
+module test15_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, output [width-1:0] q);
+generate 
+    wire [depth:0] int [width-1:0];
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        assign int[w][0] = i[w];
+        for (d = 0; d < depth; d=d+1) begin
+            \$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
+        end
+        assign q[w] = int[w][depth];
+    end
+endgenerate
+endmodule
+'''.format(i))
+
+# Test 16: neg_clk_with_enable_with_init_inferred_var_len
+for i in range(128+1,128+N+1):
+    with open('test16_%d.v' % i, 'w') as fp:
+        fp.write('''
+module test16_{0} #(parameter width=1, depth={0}) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q);
+generate 
+    reg [depth-1:0] int [width-1:0];
+
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        for (d = 0; d < depth; d=d+1)
+            initial int[w][d] <= ~((d+w) % 2);
+
+        if (depth == 1) begin
+            always @(negedge clk) if (e) int[w] <= i[w];
+            assign q[w] = int[w];
+        end
+        else begin
+            always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
+            assign q[w] = int[w][l];
+        end
+    end
+endgenerate
+endmodule
+'''.format(i))
+

architecture/synth_xilinx_srl/test17a.v

+// Check inference even when not in vector
+module test17a (input clk, input i, output q);
+generate 
+    reg a1, a2, a3, a4, a5, a6, a7, a8;
+    always @(posedge clk) a1 <= i;
+    always @(posedge clk) a2 <= a1;
+    always @(posedge clk) a3 <= a2;
+    always @(posedge clk) a4 <= a3;
+    always @(posedge clk) a5 <= a4;
+    always @(posedge clk) a6 <= a5;
+    always @(posedge clk) a7 <= a6;
+    always @(posedge clk) a8 <= a7;
+    assign q = a8;
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test17b.v

+// Check inference even when not in vector
+module test17a (input clk, input i, input e, output q);
+generate 
+   reg a1, a2, a3, a4, a5, a6, a7, a8;
+   always @(posedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
+   assign q = a8;
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test17c.v

+// Check inference even when keep attribute specified
+module test17c (input clk, input i, input e, output q);
+generate 
+    reg a1, a2, a3;
+    (* keep *) reg a4;
+    reg a5, a6, a7, a8;
+    always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
+    assign z = a8;
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test17d.v

+// Check inference even when keep attribute specified
+module test17d (input clk, input i, input e, output q);
+generate 
+    reg a1, a2;
+    (* keep *) reg a3;
+    (* keep *) reg a4;
+    reg a5, a6, a7, a8;
+    always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
+    assign q = a8;
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test17e.v

+// Check inference even when keep attribute specified
+module test17d (input clk, input i, input e, output q);
+generate 
+    reg a1, a2;
+    (* blah *) reg a3;
+    reg a4, a5, a6;
+    (* boo *) reg a7;
+    reg a8;
+    always @(negedge clk) if (e) {a8,a7,a6,a5,a4,a3,a2,a1} <= {a7,a6,a5,a4,a3,a2,a1,i};
+    assign q = a8;
+endgenerate
+endmodule
+