Add test13

architecture/synth_xilinx_srl/test13a.v

+// Check that non chain users block SRLs
+// (i.e. output port, in non flattened case)
+// sr_fixed_length_other_users_port
+module test13a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
+generate 
+    wire [depth:0] int [width-1:0];
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        assign int[w][0] = i[w];
+        for (d = 0; d < depth; d=d+1) begin
+            \$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
+        end
+        assign q[w] = int[w][depth];
+    end
+    assign state = int[0][depth:1];
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test13b.v

+// Check that non chain users block SRLs
+// (i.e. output port, in non flattened case)
+// sr_var_length_other_users_port
+module test13b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
+generate 
+    reg [depth-1:0] int [width-1:0];
+
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        for (d = 0; d < depth; d=d+1)
+            initial int[w][d] <= ~((d+w) % 2);
+
+        if (depth == 1) begin
+            always @(negedge clk) if (e) int[w] <= i[w];
+            assign q[w] = int[w];
+        end
+        else begin
+            always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
+            assign q[w] = int[w][l];
+        end
+    end
+    assign state = int[0];
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test13c.v

+// Check that non chain users block SRLs
+// (i.e. output port, in non flattened case)
+// sr_fixed_length_other_users_xor
+module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
+generate 
+    wire [depth:0] int [width-1:0];
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        assign int[w][0] = i[w];
+        for (d = 0; d < depth; d=d+1) begin
+            \$_DFFE_PP_ r(.C(clk), .D(int[w][d]), .E(1'b1), .Q(int[w][d+1]));
+        end
+        assign q[w] = int[w][depth];
+    end
+    assign state = int[0][depth:1];
+endgenerate
+endmodule

architecture/synth_xilinx_srl/test13d.v

+// Check that non chain users block SRLs
+// (i.e. output port, in non flattened case)
+// sr_var_length_other_users_xor
+module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
+generate 
+    reg [depth-1:0] int [width-1:0];
+
+    genvar w, d;
+    for (w = 0; w < width; w=w+1) begin
+        for (d = 0; d < depth; d=d+1)
+            initial int[w][d] <= ~((d+w) % 2);
+
+        if (depth == 1) begin
+            always @(negedge clk) if (e) int[w] <= i[w];
+            assign q[w] = int[w];
+        end
+        else begin
+            always @(negedge clk) if (e) int[w] <= {{ int[w][depth-2:0], i[w] }};
+            assign q[w] = int[w][l];
+        end
+    end
+    assign state = {depth{^int[0]}};
+endgenerate
+endmodule