New tests for closed issues and open bugs.

regression/Makefile

@@ -493,6 +493,58 @@ $(eval $(call template,issue_01284,issue_01284))
 #issue_01329
 $(eval $(call template,issue_01329,issue_01329))
 
+#issue_01364
+$(eval $(call template,issue_01364,issue_01364))
+
+#issue_01372
+$(eval $(call template,issue_01372,issue_01372))
+
+
+
+
+#Still open bugs (should be failed):
+#issue_00329
+$(eval $(call template,issue_00329,issue_00329))
+
+#issue_00623
+$(eval $(call template,issue_00623,issue_00623))
+
+#issue_00656
+$(eval $(call template,issue_00656,issue_00656))
+
+#issue_01014
+$(eval $(call template,issue_01014,issue_01014))
+
+#issue_01126
+$(eval $(call template,issue_01126,issue_01126))
+
+#issue_01161
+$(eval $(call template,issue_01161,issue_01161))
+
+#issue_01193
+$(eval $(call template,issue_01193,issue_01193))
+
+#issue_01206
+$(eval $(call template,issue_01206,issue_01206))
+
+#issue_01216
+$(eval $(call template,issue_01216,issue_01216))
+
+#issue_01217
+$(eval $(call template,issue_01217,issue_01217))
+
+#issue_01225
+$(eval $(call template,issue_01225,issue_01225))
+
+#issue_01259
+$(eval $(call template,issue_01259,issue_01259))
+
+#issue_01291
+$(eval $(call template,issue_01291,issue_01291))
+
+#issue_01360
+$(eval $(call template,issue_01360,issue_01360))
+
 
 
 

regression/issue_00329/top.v

+module hb_exp
+#(parameter
+ HRQW=32,
+ HRSW=32,
+ RSTRT=0,
+ REND=7,
+ ADDRW = 3,
+ NTGT=REND-RSTRT+1,
+
+ ADDR_COMP = 0,
+ BASE_ADDR_VEC = 0,
+ ADDR_MASK_VEC = 0,
+ DFF_SAMPLES   = 1
+
+)(
+
+input  clk,
+input  areset_n,
+input             init_exp_rq,
+input [ADDRW-1:0] init_exp_addr,
+input [HRQW-1:0]  init_exp_data,
+input  [NTGT-1:0] tgt_exp_ack,
+input  [NTGT-1:0] tgt_exp_err,
+input  [NTGT*HRSW-1:0] tgt_exp_data
+);
+wire [NTGT-1:0] exp_tgt_rq_samp_int    ;
+wire [NTGT-1:0] tgt_sel;
+generate
+  if(ADDR_COMP==0) begin: GEN_IND_TREE
+    assign tgt_sel = addr_dec(init_hb_addr_ff);
+  end
+  else begin: GEN_REG_TREE
+    assign tgt_sel = addr_dec_comp(init_hb_addr_ff,BASE_ADDR_VEC,ADDR_MASK_VEC);
+  end
+endgenerate
+
+assign exp_tgt_rq_samp_int = {NTGT{init_exp_rq_ff}} & tgt_sel;
+
+
+////////////////////////////////////////////////////////////////////////////////
+
+////////////////////////////////////////////////////////////////////////////////
+// Functions
+
+function  [NTGT-1:0] addr_dec(input [ADDRW-1:0] f_addr);
+integer i_tgt;
+reg [NTGT-1:0] tgt_tmp;
+begin
+  tgt_tmp={NTGT{1'b0}};
+  for(i_tgt=RSTRT;i_tgt<=REND;i_tgt=i_tgt+1) begin
+    if(f_addr==i_tgt) begin
+      tgt_tmp[i_tgt]=1'b1;
+    end
+  end
+  addr_dec=tgt_tmp;
+end
+endfunction
+
+
+function  [NTGT-1:0] addr_dec_comp(input [ADDRW-1:0] f_addr,input [NTGT*ADDRW-1:0] base_addr_in,input [NTGT*ADDRW-1:0] mask_in);
+integer i_tgt;
+reg [NTGT-1:0] tgt_tmp;
+reg [ADDRW-1:0] base_addr_arr [NTGT-1:0];
+reg [ADDRW-1:0] addr_mask_arr [NTGT-1:0];
+reg [ADDRW-1:0] end_addr_arr [NTGT-1:0];
+
+begin
+  for(i_tgt=RSTRT;i_tgt<=REND;i_tgt=i_tgt+1) begin
+    base_addr_arr[i_tgt]=base_addr_in[i_tgt*ADDRW +: ADDRW];
+    addr_mask_arr[i_tgt]=mask_in[i_tgt*ADDRW +: ADDRW];
+    end_addr_arr[i_tgt]=base_addr_arr[i_tgt] + addr_mask_arr[i_tgt];
+  end
+  tgt_tmp={NTGT{1'b0}};
+  for(i_tgt=RSTRT;i_tgt<=REND;i_tgt=i_tgt+1) begin
+    if((f_addr>=base_addr_arr[i_tgt])&&(f_addr<=end_addr_arr[i_tgt])) begin
+      tgt_tmp[i_tgt]=1'b1;
+    end
+  end
+  addr_dec_comp=tgt_tmp;
+end
+endfunction
+
+
+endmodule

regression/issue_00623/top.v

+module bidirtest (
+A, EO, Q, BI
+);
+
+inout BI;
+output Q;
+input A;
+input EO;
+
+assign BI = (EO == 1'b1) ? A : 1'bz;
+assign Q = BI;
+
+endmodule

regression/issue_00656/top.v

+module yosys_genblk_scoping #(
+                                parameter WIDTH = 6
+                                )
+    (
+     input [WIDTH-1:0]  a_i,
+     input [WIDTH-1:0]  b_i,
+
+     output [WIDTH-1:0] z_o
+     );
+
+    genvar g;
+
+    generate
+        for (g = 0; g < WIDTH; g = g + 1) begin
+            if(g > 2) begin//: blk_true
+                wire tmp;
+
+                assign tmp    = a_i[g] || b_i[g];
+                assign z_o[g] = tmp;
+            end
+            else begin
+                assign z_o[g] = a_i[g] && b_i[g];
+            end
+        end
+    endgenerate
+
+endmodule

regression/issue_01014/top.v

+module top (input [7:0] data, output [7:0] out);
+genvar n;
+generate
+    for (n=7; n>=0; n=n-1) begin
+        assign out[n] = data[7-n];
+    end
+endgenerate
+endmodule

regression/issue_01126/top.v

+module test(c);
+
+input [9:0] c;
+
+function integer a(input integer b);
+    begin
+        a = b+1;
+    end
+endfunction
+
+localparam f = 5;
+wire [a(f)-1:0] d;
+//wire [a(f)-1:0] d1;
+assign d = c[a(f)-1:0]; // wrong behavior
+localparam e = a(f);
+//assign d1 = c[e-1:0]; // correct behavior
+
+endmodule

regression/issue_01161/top.v

+module error_design(a, b, z0, z1);
+
+    input               a;
+    input               b;
+
+    output              z0, z1;
+
+    assign z0 = a;
+    assign z0 = b;
+
+    assign z1 = b;
+
+endmodule

regression/issue_01193/top.v

+module test (input e, a, output reg b);
+  always_comb
+  	if (e)
+  		b = a;
+endmodule

regression/issue_01206/top.il

+autoidx 1
+attribute \top 1
+module \top
+  wire width 1073741824 $1
+  wire width 1073741824 $2
+  process $group_0
+    sync init
+  end
+  connect $1 $2
+end

regression/issue_01216/top.v

+module top (hz100, pb, ss7, ss6, ss5, ss4, ss3, ss2, ss1, ss0, left, right, red, green, blue);
+  input hz100;
+  input [20:0] pb;
+  output [7:0] ss7;
+  output [7:0] ss6;
+  output [7:0] ss5;
+  output [7:0] ss4;
+  output [7:0] ss3;
+  output [7:0] ss2;
+  output [7:0] ss1;
+  output [7:0] ss0;
+  output [7:0] left;
+  output [7:0] right;
+  output red;
+  output green;
+  output blue;
+
+  reg [4:0] op;
+  reg [31:0] save;
+  reg [31:0] entry;
+  reg [31:0] nextresult;
+
+  wire [31:0] source = displaysave ? save : entry;
+  assign {left,right} = source[15:0];
+
+  wire [4:0] key;
+  wire pressed;
+  scankey sk(.clk(hz100), .strobe(pressed), .out(key), .in(pb));
+
+  always @ (posedge pressed)
+      begin
+        casez (key)
+          5'b0????: begin
+            entry <= {28'b0,key[3:0]};
+          end
+          5'b1????: begin
+            save <= nextresult;
+            op <= key;
+          end
+
+        endcase
+      end
+
+  always @(*)
+    case (op)
+      0: nextresult = entry;
+      default: nextresult = save;
+    endcase
+
+endmodule
+
+module scankey(clk, in, out, strobe);
+    input wire clk;
+    output wire [4:0] out;
+    output wire       strobe;
+    input  wire [20:0] in;
+    wire active;
+    reg [4:0] highest;
+
+    reg [1:0] delay;
+    always @(posedge clk)
+      delay <= delay<<1 | active;
+    assign strobe = delay[1];
+
+    assign {active,out} = in[20] == 1 ? 6'b110100 :
+                          in[19] == 1 ? 6'b110011 :
+                          in[18] == 1 ? 6'b110010 :
+                          in[17] == 1 ? 6'b110001 :
+                          in[16] == 1 ? 6'b110000 :
+                          in[15] == 1 ? 6'b101111 :
+                          in[14] == 1 ? 6'b101110 :
+                          in[13] == 1 ? 6'b101101 :
+                          in[12] == 1 ? 6'b101100 :
+                          in[11] == 1 ? 6'b101011 :
+                          in[10] == 1 ? 6'b101010 :
+                          in[ 9] == 1 ? 6'b101001 :
+                          in[ 8] == 1 ? 6'b101000 :
+                          in[ 7] == 1 ? 6'b100111 :
+                          in[ 6] == 1 ? 6'b100110 :
+                          in[ 5] == 1 ? 6'b100101 :
+                          in[ 4] == 1 ? 6'b100100 :
+                          in[ 3] == 1 ? 6'b100011 :
+                          in[ 2] == 1 ? 6'b100010 :
+                          in[ 1] == 1 ? 6'b100001 :
+                          in[ 0] == 1 ? 6'b100000 : 6'b000000;
+endmodule

regression/issue_01217/top.v

+`default_nettype none
+module mcve2(david);
+	output	reg	david;
+
+	always @(*)
+		goliath = 4;
+
+	always @(*)
+		david = goliath;
+endmodule
+`default_nettype wire

regression/issue_01225/top.v

+module top(inout pin, input dout, sel, output din);
+assign pin = sel ? dout : 1'bz;
+assign din = pin;
+endmodule

regression/issue_01259/top.v

+module top();
+	parameter W = 10;
+	wire [W-1:0] x;
+	empty #(.W(W)) empty_inst(.x(x));
+endmodule
+
+module empty#(parameter W = 0)(output wire [W-1:0] x);
+endmodule

regression/issue_01291/top.v

+module frozen(clk, out);
+
+   input        clk;
+   output reg   out;
+
+   always @(posedge clk) begin
+      out <= out;
+   end
+
+endmodule // frozen

regression/issue_01360/top.v

+module top(input clk);
+  MyInterface MyInterfaceInstance();
+endmodule
+
+interface MyInterface();
+  logic not_an_empty_interface;
+endinterface

regression/issue_01364/top.v

+module top();
+wire o;
+wire a;
+wire b;
+wire [3:0] i;
+assign o = i == 4'hb ? a:b;
+endmodule

regression/issue_01372/top.v

+////////////////////////////////////////////////////////////////////////////////
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+`default_nettype	none
+//
+module	mcvesix(i_clk, i_bits, o_char);
+	input	wire		i_clk;
+	input	wire	[6:0]	i_bits;
+	output	reg	[7:0]	o_char;
+
+	reg	[6:0]	remap	[0:127];
+
+	integer	k, newv;
+	always @(*) begin
+		for(k=0; k<128; k=k+1)
+		begin
+			newv = 0;
+// `define	BROKEN_CODE
+`ifdef	BROKEN_CODE
+			if (k[6])
+`else
+			if (k >= 64)
+`endif
+				newv = 7'h0a;
+			else
+				newv = k;
+
+			remap[k] = newv;
+		end
+	end
+
+	initial	o_char = 8'h00;
+	always @(posedge i_clk)
+		o_char <= { 1'b0, remap[i_bits] };
+
+`ifdef	FORMAL
+	reg	[7:0]	f_char;
+
+	//
+	// Here's the old encoding that "worked"
+	//
+	initial	f_char = 8'h00;
+	always @(posedge i_clk)
+	begin
+		if (i_bits[6])
+			f_char <= 8'h0a;
+		else
+			f_char <= i_bits[6:0];
+	end
+
+	//
+	// Now let's prove that the two encodings are equivalent
+	always @(*)
+		assert(f_char == o_char);
+`endif
+endmodule
+

regression/run.sh

@@ -128,7 +128,21 @@ elif [ "$1" = "issue_00502" ] ||\
 	 [ "$1" = "issue_01231" ] ||\
 	 [ "$1" = "issue_01243" ] ||\
 	 [ "$1" = "issue_01273" ] ||\
-	 [ "$1" = "issue_01329" ]; then
+	 [ "$1" = "issue_01329" ] ||\
+	 [ "$1" = "issue_01364" ] ||\
+	 [ "$1" = "issue_01372" ] ||\
+	 [ "$1" = "issue_00329" ] ||\
+	 [ "$1" = "issue_00623" ] ||\
+	 [ "$1" = "issue_01014" ] ||\
+	 [ "$1" = "issue_01126" ] ||\
+	 [ "$1" = "issue_01161" ] ||\
+	 [ "$1" = "issue_01193" ] ||\
+	 [ "$1" = "issue_01206" ] ||\
+	 [ "$1" = "issue_01216" ] ||\
+	 [ "$1" = "issue_01217" ] ||\
+	 [ "$1" = "issue_01225" ] ||\
+	 [ "$1" = "issue_01259" ] ||\
+	 [ "$1" = "issue_01291" ]; then
 
 	expected_string=""
 	expected="1"
@@ -257,7 +271,8 @@ elif [ "$1" = "issue_00502" ] ||\
 		expected_string="Executing FLATTEN pass (flatten design)."
 	elif [ "$1" = "issue_01223" ]; then
 		expected_string=" Executing CHECK pass (checking for obvious problems)."
-	elif [ "$1" = "issue_01231" ]; then
+	elif [ "$1" = "issue_01231" ] ||\
+		 [ "$1" = "issue_01364" ]; then
 		expected_string="Successfully finished Verilog frontend."
 	elif [ "$1" = "issue_01243" ]; then
 		expected_string="assign y = reg_assign;"
@@ -265,6 +280,40 @@ elif [ "$1" = "issue_00502" ] ||\
 		expected_string="\$_MUX8_                         9"
 	elif [ "$1" = "issue_01329" ]; then
 		expected_string="\$mux                            1"
+	elif [ "$1" = "issue_01372" ]; then
+		expected_string="input \\[1:0\\] s"
+	elif [ "$1" = "issue_00329" ]; then
+		expected_string="wire \\[-1"
+	elif [ "$1" = "issue_00623" ]; then
+		expected_string="IOBUF _4_"
+	elif [ "$1" = "issue_00656" ]; then
+		expected_string="Successfully finished Verilog frontend."
+	elif [ "$1" = "issue_01014" ]; then
+		expected_string="Successfully finished Verilog frontend."
+	elif [ "$1" = "issue_01126" ]; then
+		expected_string="assign d = c\\[5:0\\]"
+	elif [ "$1" = "issue_01161" ]; then
+		expected_string="assign z0 = b"
+	elif [ "$1" = "issue_01193" ]; then
+		expected_string="cell \$dlatch"
+		expected="0"
+	elif [ "$1" = "issue_01206" ]; then
+		expected_string="Executing PROC_INIT pass"
+	elif [ "$1" = "issue_01216" ]; then
+		expected_string="ERROR: Assert"
+		expected="0"
+	elif [ "$1" = "issue_01217" ]; then
+		expected_string="is implicitly declared."
+		expected="0"
+	elif [ "$1" = "issue_01225" ]; then
+		expected_string="cell \OBUFT"
+	elif [ "$1" = "issue_01259" ]; then
+		expected_string="Executing SMT2 backend"
+	elif [ "$1" = "issue_01291" ]; then
+		expected_string="connect \\\out 1'x"
+		expected="0"
+	elif [ "$1" = "issue_01360" ]; then
+		expected_string="Executing BLIF backend"
 	fi
 
 	if [ "$1" = "issue_01118" ]; then

regression/scripts/issue_00329.ys

+read_verilog -mem2reg ../top.v
+write_verilog result.log

regression/scripts/issue_00623.ys

+read_verilog ../top.v
+tribuf -logic
+synth -top bidirtest
+iopadmap -bits -inpad IBUF O:PAD -outpad OBUF I:PAD -tinoutpad IOBUF ENA:O:I:PAD bidirtest
+write_verilog -noattr result.log

regression/scripts/issue_00656.ys

+tee -o result.log read_verilog ../top.v

regression/scripts/issue_01014.ys

+tee -o result.log read_verilog ../top.v
+synth
+write_verilog synth.v

regression/scripts/issue_01126.ys

+read_verilog ../top.v
+write_verilog result.log
+#write_json test_synth.json

regression/scripts/issue_01161.ys

+read_verilog ../top.v
+
+hierarchy
+proc
+
+write_ilang error_design.proc.il
+show -format svg -prefix error_design.proc error_design
+write_verilog result_old.log
+
+opt_clean
+write_ilang error_design.opt_clean.il
+show -format svg -prefix error_design.opt_clean error_design
+write_verilog result.log

regression/scripts/issue_01193.ys

+read_verilog -sv ../top.v
+proc
+
+tee -o result.log dump

regression/scripts/issue_01206.ys

+read_ilang ../top.il
+tee -o result.log proc_init

regression/scripts/issue_01216.ys

+read_verilog ../top.v
+tee -o result.log synth_ice40 -top top
+tee -o result.log write_blif test.blif

regression/scripts/issue_01217.ys

+tee -o result.log read_verilog ../top.v

regression/scripts/issue_01225.ys

+tee -o result.log read_verilog ../top.v
+synth_xilinx
+tee -o result.log dump

regression/scripts/issue_01259.ys

+tee -o result.log read_verilog ../top.v
+hierarchy -top top
+tee -o result.log write_smt2

regression/scripts/issue_01291.ys

+tee -o result.log read_verilog ../top.v
+prep -top frozen
+tee -o result.log dump

regression/scripts/issue_01360.ys

+read_verilog -sv ../top.v;
+tee -o result.log synth_ice40 -blif out.blif

regression/scripts/issue_01364.ys

+tee -o result.log read_verilog ../top.v
+

regression/scripts/issue_01372.ys

+read -define BROKEN_CODE
+read -formal ../top.v
+prep -top mcvesix
+write_verilog result.log