Review and update tests for issues 961-1231

regression/Makefile

@@ -17,62 +17,6 @@ clean::
 ))
 endef
 
-#issue_00961
-$(eval $(call template,issue_00961,issue_00961))
-
-#issue_00968
-$(eval $(call template,issue_00968,issue_00968))
-
-#issue_00981
-$(eval $(call template,issue_00981,issue_00981))
-
-#issue_00982
-$(eval $(call template,issue_00982,issue_00982))
-
-#issue_00987
-$(eval $(call template,issue_00987,issue_00987))
-
-#issue_00993
-$(eval $(call template,issue_00993,issue_00993))
-
-#issue_00997
-$(eval $(call template,issue_00997,issue_00997))
-
-#issue_01002
-$(eval $(call template,issue_01002,issue_01002))
-
-#issue_01016
-$(eval $(call template,issue_01016,issue_01016))
-
-#issue_01022
-$(eval $(call template,issue_01022,issue_01022))
-
-#issue_01023
-$(eval $(call template,issue_01023,issue_01023))
-
-#issue_01033
-$(eval $(call template,issue_01033,issue_01033))
-
-#issue_01034
-$(eval $(call template,issue_01034,issue_01034))
-
-#issue_01040
-$(eval $(call template,issue_01040,issue_01040))
-
-#issue_01047
-$(eval $(call template,issue_01047,issue_01047))
-
-#issue_01063
-$(eval $(call template,issue_01063,issue_01063))
-
-#issue_01065
-$(eval $(call template,issue_01065,issue_01065))
-
-#issue_01070
-$(eval $(call template,issue_01070,issue_01070))
-
-#issue_01084
-$(eval $(call template,issue_01084,issue_01084))
 
 #issue_01091
 $(eval $(call template,issue_01091,issue_01091))
@@ -135,9 +79,6 @@ $(eval $(call template,issue_01372,issue_01372))
 
 
 #Still open bugs (should be failed):
-#issue_01014
-$(eval $(call template,issue_01014,issue_01014))
-
 #issue_01126
 $(eval $(call template,issue_01126,issue_01126))
 

regression/scripts/issue_00987.ys

-tee -a result.log read_verilog -sv ../top.v
-
-

regression/scripts/issue_01084.ys

-tee -o result.log read_verilog ../top.v

regression_revised/Makefile

@@ -383,6 +383,66 @@ $(eval $(call template,issue_00955,issue_00955))
 #issue_00956
 $(eval $(call template,issue_00956,issue_00956))
 
+#issue_00961
+$(eval $(call template,issue_00961,issue_00961))
+
+#issue_00968
+$(eval $(call template,issue_00968,issue_00968))
+
+#issue_00981
+$(eval $(call template,issue_00981,issue_00981))
+
+#issue_00982
+$(eval $(call template,issue_00982,issue_00982))
+
+#issue_00987
+$(eval $(call template,issue_00987,issue_00987))
+
+#issue_00993
+$(eval $(call template,issue_00993,issue_00993))
+
+#issue_00997
+$(eval $(call template,issue_00997,issue_00997))
+
+#issue_01002
+$(eval $(call template,issue_01002,issue_01002))
+
+#issue_01014
+$(eval $(call template,issue_01014,issue_01014))
+
+#issue_01016
+$(eval $(call template,issue_01016,issue_01016))
+
+#issue_01022
+$(eval $(call template,issue_01022,issue_01022))
+
+#issue_01023
+$(eval $(call template,issue_01023,issue_01023))
+
+#issue_01033
+$(eval $(call template,issue_01033,issue_01033))
+
+#issue_01034
+$(eval $(call template,issue_01034,issue_01034))
+
+#issue_01040
+$(eval $(call template,issue_01040,issue_01040))
+
+#issue_01047
+$(eval $(call template,issue_01047,issue_01047))
+
+#issue_01063
+$(eval $(call template,issue_01063,issue_01063_fail))
+
+#issue_01065
+$(eval $(call template,issue_01065,issue_01065))
+
+#issue_01070
+$(eval $(call template,issue_01070,issue_01070))
+
+#issue_01084
+$(eval $(call template,issue_01084,issue_01084))
+
 #Still open bugs (should be failed):
 #issue_00329
 $(eval $(call template,issue_00329,issue_00329))

regression/scripts/issue_01065.ys → regression_revised/issue_00961/issue_00961.ys

 read_verilog ../top.v
 proc
-tee -o result.log opt -fast

regression_revised/issue_00968/issue_00968.pat

+assign o_value = { 4'hx, i_value }

regression/scripts/issue_00968.ys → regression_revised/issue_00968/issue_00968.ys

 read -sv ../top.v
 hierarchy -top mcve1
 synth
-write_verilog result.log
-
+write_verilog result.out

regression/scripts/issue_00981.ys → regression_revised/issue_00981/issue_00981.ys

 read_verilog ../top.v
-tee -a result.log synth_ice40
+tee -a result.out synth_ice40
 

regression_revised/issue_00982/issue_00982.pat

+parameter \\INIT 1'0

regression/scripts/issue_00982.ys → regression_revised/issue_00982/issue_00982.ys

 read_verilog ../top.v
 synth_xilinx
-tee -a result.log dump t:FDRE
-
+select -assert-count 3 t:FDRE
+tee -a result.out dump t:FDRE

regression_revised/issue_00987/issue_00987.ys

+read_verilog -sv ../top.v

regression/scripts/issue_00993.ys → regression_revised/issue_00993/issue_00993.ys

 read -formal ../top.v
 hierarchy -top top
-tee -a result.log synth
+synth
 #write_verilog rtl_yosys.v

regression_revised/issue_00997/issue_00997.pat

+reg \\reg10_reg\[0\]  = 1'h0;

regression/scripts/issue_00997.ys → regression_revised/issue_00997/issue_00997.ys

 read -formal ../top.v
 hierarchy -top top
 synth
-write_verilog -noattr result.log
+write_verilog -noattr result.out

regression_revised/issue_01002/issue_01002.pat

+Estimated number of LCs:         87

regression/scripts/issue_01002.ys → regression_revised/issue_01002/issue_01002.ys

 read -sv ../top.v
 hierarchy -top onehot -chparam LG 7
-tee -a result.log synth_xilinx
-
+tee -a result.out synth_xilinx

regression/scripts/issue_01016.ys → regression_revised/issue_01016/issue_01016.ys

@@ -2,4 +2,3 @@ read_verilog -sv ../top.v
 proc
 wreduce -keepdc
 select -assert-count 1 t:$mux
-

regression/scripts/issue_01023.ys → regression_revised/issue_01023/issue_01023.ys

 read_verilog -icells ../top.v
-tee -a result.log techmap
-
+techmap

regression/scripts/issue_01033.ys → regression_revised/issue_01033/issue_01033.ys

 read_verilog ../top.v
 synth_xilinx
 select -assert-none t:RAM64X1D
-

regression/scripts/issue_01034.ys → regression_revised/issue_01034/issue_01034.ys

-read_verilog ../top.v
+read_verilog -DUNPACKED ../top.v
 synth_xilinx -nodram
 select -assert-none t:FDRE
 

regression_revised/issue_01040/issue_01040.pat

+.subckt dut_sub a\[2\]=a\[2\] a\[3\]=a\[3\] a\[4\]=a\[4\] a\[5\]=a\[5\] a\[6\]=a\[6\] a\[7\]=a\[7\] a\[8\]=a\[8\] a\[9\]=a\[9\] a\[10\]=a\[10\] a\[11\]=a\[11\] a\[12\]=a\[12\] a\[13\]=a\[13\] a\[14\]=a\[14\] a\[15\]=a\[15\] a\[16\]=a\[16\] a\[17\]=a\[17\] a\[18\]=a\[18\] a\[19\]=a\[19\] a\[20\]=a\[20\] a\[21\]=a\[21\] a\[22\]=a\[22\] a\[23\]=a\[23\] a\[24\]=a\[24\] a\[25\]=a\[25\] a\[26\]=a\[26\] a\[27\]=a\[27\] a\[28\]=a\[28\] a\[29\]=a\[29\] a\[30\]=a\[30\] a\[31\]=a\[31\] a\[32\]=a\[32\] a_l\[2\]=a_l\[2\] a_l\[3\]=a_l\[3\] a_l\[4\]=a_l\[4\] a_l\[5\]=a_l\[5\] a_l\[6\]=a_l\[6\] a_l\[7\]=a_l\[7\] a_l\[8\]=a_l\[8\] a_l\[9\]=a_l\[9\] a_l\[10\]=a_l\[10\] a_l\[11\]=a_l\[11\] a_l\[12\]=a_l\[12\] a_l\[13\]=a_l\[13\] a_l\[14\]=a_l\[14\] a_l\[15\]=a_l\[15\] a_l\[16\]=a_l\[16\] a_l\[17\]=a_l\[17\] a_l\[18\]=a_l\[18\] a_l\[19\]=a_l\[19\] a_l\[20\]=a_l\[20\] a_l\[21\]=a_l\[21\] a_l\[22\]=a_l\[22\] a_l\[23\]=a_l\[23\] a_l\[24\]=a_l\[24\] a_l\[25\]=a_l\[25\] a_l\[26\]=a_l\[26\] a_l\[27\]=a_l\[27\] a_l\[28\]=a_l\[28\] a_l\[29\]=a_l\[29\] a_l\[30\]=a_l\[30\] a_l\[31\]=a_l\[31\] a_l\[32\]=a_l\[32\] clk=clk

regression/scripts/issue_01040.ys → regression_revised/issue_01040/issue_01040.ys

 read_verilog ../top.v
 synth
-write_blif result.log
+write_blif result.out

regression_revised/issue_01063/issue_01063_fail.pat

+ERROR: Gate cell u_mid8 not found in module top.

regression_revised/issue_01065/issue_01065.ys

+read_verilog ../top.v
+proc
+tee -o result.out opt -fast

regression_revised/issue_01065/issue_01065_n.ys

+Warning: Driver-driver conflict for \\q between cell u.i and constant 1'0 in top: Resolved using constant.

regression/scripts/issue_00961.ys → regression_revised/issue_01084/issue_01084.ys

 read_verilog ../top.v
-tee -a result.log proc
-