Skip to content

Y
yosys-tests
Commit 4b51047c by SergeyDegtyar
Options

Review and update tests for issues 826-956

parent 7c5101bf
Showing with 100 additions and 133 deletions
regression/Makefile
......@@ -17,66 +17,6 @@ clean::
))
endef
#issue_00826
$(eval $(call template,issue_00826,issue_00826))
#issue_00831
$(eval $(call template,issue_00831,issue_00831))
#issue_00835
$(eval $(call template,issue_00835,issue_00835))
#issue_00857
$(eval $(call template,issue_00857,issue_00857))
#issue_00862
$(eval $(call template,issue_00862,issue_00862))
#issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
$(eval $(call template,issue_00865,issue_00865))
#issue_00867
$(eval $(call template,issue_00867,issue_00867))
#issue_00870
$(eval $(call template,issue_00870,issue_00870))
#issue_00873
$(eval $(call template,issue_00873,issue_00873))
#issue_00888
$(eval $(call template,issue_00888,issue_00888))
#issue_00896
$(eval $(call template,issue_00896,issue_00896))
#issue_00922
$(eval $(call template,issue_00922,issue_00922))
#issue_00931
$(eval $(call template,issue_00931,issue_00931))
#issue_00935
$(eval $(call template,issue_00935,issue_00935))
#issue_00938
$(eval $(call template,issue_00938,issue_00938))
#issue_00940
$(eval $(call template,issue_00940,issue_00940))
#issue_00948
$(eval $(call template,issue_00948,issue_00948))
#issue_00954
$(eval $(call template,issue_00954,issue_00954))
#issue_00955
$(eval $(call template,issue_00955,issue_00955))
#issue_00956
$(eval $(call template,issue_00956,issue_00956))
#issue_00961
$(eval $(call template,issue_00961,issue_00961))
......
regression/issue_00831/top.v deleted 100644 → 0
`default_nettype none
module A;
parameter P = 0;
endmodule
module top;
A inst_i();
defparam inst_i.P = 1;
endmodule
regression/issue_00896/testbench.v deleted 100644 → 0
`include "../outreg.v"
module tb;
reg fast_clk, slow_clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, tb);
repeat (80) @(posedge slow_clk);
$display("OKAY");
$finish;
end
always #4 fast_clk = (fast_clk === 1'b0);
always #12 slow_clk = (slow_clk === 1'b0);
reg [7:0] wdata = 1;
always @(posedge fast_clk) wdata <= {wdata[6:0], wdata[7] ^ wdata[2]};
reg [3:0] waddr = 0;
always @(posedge fast_clk) waddr <= waddr + 1'b1;
reg [3:0] raddr = 0;
always @(posedge slow_clk) raddr <= raddr + 1'b1;
wire [3:0] rdata, rdata_postsyn;
dut dut_i(
.fast_clk(fast_clk), .slow_clk(slow_clk),
.raddr(raddr), .waddr(waddr), .wen(1'b1),
.wdata(wdata[3:0]), .rdata(rdata)
);
dut_syn dut_syn_i(
.fast_clk(fast_clk), .slow_clk(slow_clk),
.raddr(raddr), .waddr(waddr), .wen(1'b1),
.wdata(wdata[3:0]), .rdata(rdata_postsyn)
);
always @(posedge fast_clk)
if (rdata_postsyn != rdata) begin
$display("ERROR");
$finish;
end
endmodule
regression/scripts/issue_00826.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_00862.ys deleted 100644 → 0
tee -o result.log read_verilog -sv ../top.v
regression/scripts/issue_00896.ys deleted 100644 → 0
read_verilog ../outreg.v
synth_ecp5
rename dut dut_syn
write_verilog -norename synth.v
regression_revised/Makefile
......@@ -323,6 +323,66 @@ $(eval $(call template,issue_00814,issue_00814_fail))
#issue_00823
$(eval $(call template,issue_00823,issue_00823))
#issue_00826
$(eval $(call template,issue_00826,issue_00826))
#issue_00831
$(eval $(call template,issue_00831,issue_00831))
#issue_00835
$(eval $(call template,issue_00835,issue_00835))
#issue_00857
$(eval $(call template,issue_00857,issue_00857))
#issue_00862
$(eval $(call template,issue_00862,issue_00862))
#issue_00865
$(eval $(call template,issue_00865,issue_00865))
#issue_00867
$(eval $(call template,issue_00867,issue_00867))
#issue_00870
$(eval $(call template,issue_00870,issue_00870))
#issue_00873
$(eval $(call template,issue_00873,issue_00873))
#issue_00888
$(eval $(call template,issue_00888,issue_00888))
#issue_00896
$(eval $(call template,issue_00896,issue_00896))
#issue_00922
$(eval $(call template,issue_00922,issue_00922))
#issue_00931
$(eval $(call template,issue_00931,issue_00931))
#issue_00935
$(eval $(call template,issue_00935,issue_00935))
#issue_00938
$(eval $(call template,issue_00938,issue_00938))
#issue_00940
$(eval $(call template,issue_00940,issue_00940))
#issue_00948
$(eval $(call template,issue_00948,issue_00948))
#issue_00954
$(eval $(call template,issue_00954,issue_00954))
#issue_00955
$(eval $(call template,issue_00955,issue_00955))
#issue_00956
$(eval $(call template,issue_00956,issue_00956))
#Still open bugs (should be failed):
#issue_00329
$(eval $(call template,issue_00329,issue_00329))
......
regression_revised/issue_00831/issue_00831.pat 0 → 100644
yosys-smt2-memory rom 2 8 1 0 async
regression/scripts/issue_00831.ys → regression_revised/issue_00831/issue_00831.ys
read_verilog ../top.v
prep
tee -o result.log write_smt2 test.smt2
write_smt2 result.out
regression_revised/issue_00831/top.v 0 → 100644
module test(input [1:0] addr, output [7:0] o);
reg [7:0] rom [0:3];
initial begin
rom[0] <= 8'b 0100100x;
rom[1] <= 8'b 00100x01;
rom[2] <= 8'b 010x0010;
rom[3] <= 8'b 0x010100;
end
assign o = rom[addr];
endmodule
regression/scripts/issue_00857.ys → regression_revised/issue_00857/issue_00857.ys
......@@ -2,4 +2,3 @@ read_verilog ../top.v
synth -top top
select -assert-count 1 t:$_DFF_P_
select -assert-none t:$_DFF_P_ %% t:* %D
regression/scripts/issue_00870.ys → regression_revised/issue_00870/issue_00870.ys
......@@ -10,5 +10,4 @@ opt -full;
write_verilog multimux_out_2.v
delete;
tee -o result.log read_verilog multimux_out_2.v
read_verilog multimux_out_2.v
regression/scripts/issue_00888.ys → regression_revised/issue_00888/issue_00888.ys
read_verilog ../top.v
read_verilog -DBROKEN ../top.v
synth_xilinx
select -assert-count 4 t:FDRE
regression_revised/issue_00896/issue_00896.ys 0 → 100644
read_verilog ../outreg.v
hierarchy -top dut
proc
memory -nomap
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd dut
stat
select -assert-count 1 t:TRELLIS_DPR16X4
select -assert-count 4 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF t:TRELLIS_DPR16X4 %% t:* %D
regression/scripts/issue_00948.ys → regression_revised/issue_00948/issue_00948.ys
......@@ -3,4 +3,4 @@ synth
opt_expr
write_verilog bug.v
delete
tee -a result.log read_verilog bug.v
read_verilog bug.v
regression/scripts/issue_00954.ys → regression_revised/issue_00954/issue_00954.ys
......@@ -3,5 +3,4 @@ synth
abc
eval -set addr 24
aigmap
tee -a result.log eval -set addr 24
tee -a result.out eval -set addr 24
regression_revised/issue_00955/issue_00955.pat 0 → 100644
Eval result: \\out = 8'00001000.
regression/scripts/issue_00955.ys → regression_revised/issue_00955/issue_00955.ys
read_verilog ../top.v
synth
eval -set addr 24
tee -a result1.out eval -set addr 24
abc
tee -a result.log eval -set addr 24
tee -a result.out eval -set addr 24
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment