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lvzhengyang
yosys-tests
Commits
639715e9
Commit
639715e9
authored
Jun 28, 2019
by
Eddie Hung
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Use 'script -select' to check area as we go along, not all at end
parent
3c5df7dd
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2 changed files
with
13 additions
and
9 deletions
+13
-9
architecture/synth_xilinx_mux/assert_area.py
+9
-5
architecture/synth_xilinx_mux/run-test.sh
+4
-4
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architecture/synth_xilinx_mux/assert_area.py
View file @
639715e9
...
...
@@ -42,9 +42,13 @@ for fn in glob.glob('*.v'):
assert
N
in
area
bn
,
_
=
os
.
path
.
splitext
(
fn
)
print
(
'design -reset'
)
print
(
'read_verilog {0}.out/{0}_syn0.v'
.
format
(
bn
))
for
r
,
v
in
zip
([
'LUT1'
,
'LUT2'
,
'LUT3'
,
'LUT4'
,
'LUT5'
,
'LUT6'
,
'MUXF7'
,
'MUXF8'
],
area
[
N
]):
print
(
'select t:{0} -assert-count {1}'
.
format
(
r
,
v
*
W
))
with
open
(
fn
,
'a'
)
as
f
:
assert_area
=
[
'select t:{0} -assert-count {1}'
.
format
(
r
,
v
*
W
)
for
r
,
v
in
zip
([
'LUT1'
,
'LUT2'
,
'LUT3'
,
'LUT4'
,
'LUT5'
,
'LUT6'
,
'MUXF7'
,
'MUXF8'
],
area
[
N
])]
print
(
'''
`ifndef _AUTOTB
module
\
$__test ;
wire [4095:0] assert_area = "
%
s";
endmodule
`endif
'''
%
'; '
.
join
(
assert_area
),
file
=
f
)
architecture/synth_xilinx_mux/run-test.sh
View file @
639715e9
...
...
@@ -22,7 +22,7 @@ wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchm
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py
-O
generate_large.py
-o
/dev/null
python3 generate_small.py
python3 generate_large.py
${
MAKE
:-
make
}
-f
../../../../tools/autotest.mk
$seed
*
.v
EXTRA_FLAGS
=
"-p 'synth_xilinx -abc9 -widemux 5' -l ../../../../../techlibs/xilinx/cells_sim.v"
python3 ../assert_area.py
>
assert_area.ys
yosys
-q
assert_area.ys
python3 ../assert_area.py
${
MAKE
:-
make
}
-f
../../../../tools/autotest.mk
$seed
*
.v
EXTRA_FLAGS
=
"
\
-p 'synth_xilinx -abc9 -widemux 5; script -select
\$
__test/w:assert_area'
\
-l ../../../../../techlibs/xilinx/cells_sim.v"
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