Commit 639715e9 by Eddie Hung

Use 'script -select' to check area as we go along, not all at end

parent 3c5df7dd
......@@ -42,9 +42,13 @@ for fn in glob.glob('*.v'):
assert N in area
bn,_ = os.path.splitext(fn)
print('design -reset')
print('read_verilog {0}.out/{0}_syn0.v'.format(bn))
for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N]):
print('select t:{0} -assert-count {1}'.format(r,v*W))
with open(fn, 'a') as f:
assert_area = ['select t:{0} -assert-count {1}'.format(r,v*W) for r,v in zip(['LUT1','LUT2','LUT3','LUT4','LUT5','LUT6','MUXF7','MUXF8'], area[N])]
print('''
`ifndef _AUTOTB
module \$__test ;
wire [4095:0] assert_area = "%s";
endmodule
`endif
''' % '; '.join(assert_area), file=f)
......@@ -22,7 +22,7 @@ wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchm
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_large/mux/generate.py -O generate_large.py -o /dev/null
python3 generate_small.py
python3 generate_large.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'synth_xilinx -abc9 -widemux 5' -l ../../../../../techlibs/xilinx/cells_sim.v"
python3 ../assert_area.py > assert_area.ys
yosys -q assert_area.ys
python3 ../assert_area.py
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
-p 'synth_xilinx -abc9 -widemux 5; script -select \$__test/w:assert_area'\
-l ../../../../../techlibs/xilinx/cells_sim.v"
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