Merge remote-tracking branch 'origin/master' into xc7mux

architecture/Makefile

@@ -19,52 +19,61 @@ endef
 
 #achronix
 $(eval $(call template,synth_achronix,synth_achronix synth_achronix_top synth_achronix_vout synth_achronix_run synth_achronix_noflatten synth_achronix_retime))
+$(eval $(call template,synth_achronix_error,synth_achronix_fully_selected))
 
 #anlogic
 $(eval $(call template,synth_anlogic,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
 $(eval $(call template,synth_anlogic_fulladder,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime))
 $(eval $(call template,synth_anlogic_mem,synth_anlogic synth_anlogic_top synth_anlogic_edif synth_anlogic_json synth_anlogic_run synth_anlogic_noflatten synth_anlogic_retime anlogic_determine_init_eqn))
+$(eval $(call template,synth_anlogic_error,synth_anlogic_fully_selected))
 
 #coolrunner2
 $(eval $(call template,synth_coolrunner2,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
 $(eval $(call template,synth_coolrunner2_fulladder,synth_coolrunner2 synth_coolrunner2_top synth_coolrunner2_vout synth_coolrunner2_run synth_coolrunner2_noflatten synth_coolrunner2_retime))
+$(eval $(call template,synth_coolrunner2_error,synth_coolrunner2_fully_selected))
 
 #easic - issue #920
+# we do not have eTools anymore available, commented until aquired
 #$(eval $(call template,synth_easic,synth_easic synth_easic_top synth_easic_vlog synth_easic_run synth_easic_noflatten synth_easic_retime))
+$(eval $(call template,synth_easic_error,synth_easic_fully_selected))
 
 #ecp5
 $(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
 $(eval $(call template,synth_ecp5_wide_ffs,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
+$(eval $(call template,synth_ecp5_error,synth_ecp5_fully_selected))
 
 #gowin
 $(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten ))
 $(eval $(call template,synth_gowin_mem,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten ))
+$(eval $(call template,synth_gowin_error,synth_gowin_fully_selected ))
 
 #ice40
 $(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
 $(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
 $(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
+$(eval $(call template,synth_ice40_error,synth_ice40_fully_selected))
 
 #intel
 $(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_noiopads synth_intel_nobram synth_intel_max10 ))
 $(eval $(call template,synth_intel_cycloneiv,synth_intel_cycloneiv  ))
 $(eval $(call template,synth_intel_cycloneive,synth_intel_cycloneive   ))
-
-# - issue #921
-#../../../../../techlibs/intel/cyclonev/cells_sim.v:88: error: Unable to bind wire/reg/memory `upper_mask_value' in `testbench.uut._05_.lut5'
-#$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
+$(eval $(call template,synth_intel_cyclonev ,synth_intel_cyclonev ))
 $(eval $(call template,synth_intel_cyclone10,synth_intel_cyclone10 ))
 $(eval $(call template,synth_intel_a10gx ,synth_intel_a10gx ))
+$(eval $(call template,synth_intel_error ,synth_intel_fully_selected synth_intel_invalid_family ))
 
 #sf2
 $(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf2_json synth_sf2_run synth_sf2_noflatten synth_sf2_retime synth_sf2_vlog synth_sf2_noiobs synth_sf2_clkbuf ))
+$(eval $(call template,synth_sf2_error,synth_sf2_fully_selected ))
 
 #xilinx
-$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr))
+$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl))
+$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch ))
 $(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
 
 #greenpak4
 $(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
 $(eval $(call template,synth_greenpak4_wide_ffs,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
+$(eval $(call template,synth_greenpak4_error,synth_greenpak4_fully_selected synth_greenpak4_invalid_part))
 
 .PHONY: all clean

architecture/common.v

 module assert_dff(input clk, input test, input pat);
     always @(posedge clk)
     begin
+        #1;
         if (test != pat)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time);
@@ -12,7 +13,7 @@ endmodule
 module assert_tri(input en, input A, input B);
     always @(posedge en)
     begin
-        //#1;
+        #1;
         if (A !== B)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
@@ -24,7 +25,7 @@ endmodule
 module assert_Z(input clk, input A);
     always @(posedge clk)
     begin
-        //#1;
+        #1;
         if (A === 1'bZ)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);

architecture/scripts/synth_achronix_fully_selected.ys

+read_verilog ../top.v
+select top2
+synth_achronix
+write_verilog synth.v

architecture/scripts/synth_anlogic_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_anlogic
+write_verilog synth.v

architecture/scripts/synth_coolrunner2_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_coolrunner2
+write_verilog synth.v

architecture/scripts/synth_easic_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_easic
+write_verilog synth.v

architecture/scripts/synth_ecp5_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_ecp5
+write_verilog synth.v

architecture/scripts/synth_gowin_fully_selected.ys

+read_verilog ../top.v
+select top2
+synth_gowin
+write_verilog synth.v

architecture/scripts/synth_greenpak4_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_greenpak4
+write_verilog synth.v

architecture/scripts/synth_greenpak4_invalid_part.ys

+read_verilog ../top.v
+synth_greenpak4 -part ggg
+write_verilog synth.v

architecture/scripts/synth_ice40_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_ice40
+write_verilog synth.v

architecture/scripts/synth_intel_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_intel
+write_verilog synth.v

architecture/scripts/synth_intel_invalid_family.ys

+read_verilog ../top.v
+synth_intel -family u
+write_verilog synth.v

architecture/scripts/synth_sf2_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_sf2
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xc6s.ys

+read_verilog ../top.v
+synth_xilinx -arch xc6s
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xc7.ys

+read_verilog ../top.v
+synth_xilinx -arch xc7
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xcu.ys

+read_verilog ../top.v
+synth_xilinx -arch xcu
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xcup.ys

+read_verilog ../top.v
+synth_xilinx -arch xcup
+write_verilog synth.v

architecture/scripts/synth_xilinx_fully_selected.ys

+read_verilog ../top.v
+select dffe
+synth_xilinx
+write_verilog synth.v

architecture/scripts/synth_xilinx_invalid_arch.ys

+read_verilog ../top.v
+synth_xilinx -arch zinq7000
+write_verilog synth.v

architecture/scripts/synth_xilinx_nobram.ys

+read_verilog ../top.v
+synth_xilinx -nobram
+write_verilog synth.v

architecture/scripts/synth_xilinx_nodram.ys

+read_verilog ../top.v
+synth_xilinx -nodram
+write_verilog synth.v

architecture/scripts/synth_xilinx_nosrl.ys

+read_verilog ../top.v
+synth_xilinx -nosrl
+write_verilog synth.v

architecture/scripts/synth_xilinx_nosrt.ys

+read_verilog ../top.v
+synth_xilinx -nosrl
+write_verilog synth.v

architecture/synth_achronix_error/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_achronix_error/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module top2
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_anlogic/testbench.v

@@ -11,10 +11,10 @@ module testbench;
             #5 clk = 0;
         end
 
-        $display("OKAY");    
+        $display("OKAY");
     end
-   
-    
+
+
     reg [2:0] dinA = 0;
     wire doutB,doutB1,doutB2,doutB3,doutB4;
 	reg dff,ndff,adff,adffn,dffe = 0;
@@ -30,12 +30,12 @@ module testbench;
         .b3 (doutB3 ),
         .b4 (doutB4 )
     );
-    
+
     always @(posedge clk) begin
     #3;
     dinA <= dinA + 1;
     end
-	
+
 	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
 		if ( dinA[2] )
 			dff <= 1'b0;
@@ -43,7 +43,7 @@ module testbench;
 			dff <= 1'b1;
 		else
             dff <= dinA[0];
-    
+
     always @( negedge clk, negedge dinA[1], negedge dinA[2] )
 		if ( !dinA[2] )
 			ndff <= 1'b0;
@@ -51,27 +51,27 @@ module testbench;
 			ndff <= 1'b1;
 		else
             ndff <= dinA[0];
-            
+
     always @( posedge clk, posedge dinA[2] )
 		if ( dinA[2] )
 			adff <= 1'b0;
 		else
             adff <= dinA[0];
-            
+
     always @( posedge clk, negedge dinA[2] )
 		if ( !dinA[2] )
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
-            
+
 	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
     assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
-    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
     assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
     assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
-    
+
 endmodule

architecture/synth_anlogic/top.v

@@ -5,9 +5,9 @@ module adff
     end
 	always @( posedge clk, posedge clr )
 		if ( clr )
-`ifndef BUG        
+`ifndef BUG
 			q <= 1'b0;
-`else        
+`else
 			q <= d;
 `endif
 		else
@@ -21,9 +21,9 @@ module adffn
     end
 	always @( posedge clk, negedge clr )
 		if ( !clr )
-`ifndef BUG        
+`ifndef BUG
 			q <= 1'b0;
-`else        
+`else
 			q <= d;
 `endif
 		else
@@ -35,11 +35,11 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
-`ifndef BUG        
+`ifndef BUG
 			q <= d;
-`else        
+`else
 			q <= 1'b0;
 `endif
 endmodule

architecture/synth_anlogic_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk)
+		if ( dinA[2] )
+            dffe <= dinA[0];
+
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+
+endmodule

architecture/synth_anlogic_error/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk)
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_coolrunner2_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_coolrunner2_error/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_easic_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_easic_error/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_ecp5/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_ecp5/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_ecp5_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_ecp5_error/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk)
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_gowin_error/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_gowin_error/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_gowin_mem/testbench.v

@@ -22,30 +22,11 @@ module testbench;
 	reg mem_init = 0;
 
     top uut (
-    data_a[0],
-    data_a[1],
-    data_a[2],
-    data_a[3],
-    data_a[4],
-    data_a[5],
-    data_a[6],
-    data_a[7],
-	addr_a[0],
-	addr_a[1],
-	addr_a[2],
-	addr_a[3],
-	addr_a[4],
-	addr_a[5],
+        data_a,
+	addr_a,
 	we_a,
 	clk,
-	q_a[0],
-	q_a[1],
-	q_a[2],
-	q_a[3],
-	q_a[4],
-	q_a[5],
-	q_a[6],
-	q_a[7]
+	q_a
     );
 
     always @(posedge clk) begin

architecture/synth_greenpak4/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk)
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_greenpak4/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk)
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_greenpak4_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk)
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_greenpak4_error/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk)
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_ice40/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_ice40/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_ice40_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_ice40_error/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_ice40_mem/top.v

@@ -24,7 +24,7 @@ module top
 	SB_RAM40_4K #(
     .READ_MODE(2'h1),
     .WRITE_MODE(2'h1),
-    .INIT_FILE("init.txt")
+    .INIT_FILE("../init.txt")
   ) \ram.0.0.0  (
     .MASK(16'hxxxx),
     .RADDR({ 5'h00, addr_a }),

architecture/synth_intel_error/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_intel_error/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

architecture/synth_sf2_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_sf2_error/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge en )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

architecture/synth_xilinx/testbench.v

@@ -63,8 +63,8 @@ module testbench;
 			adffn <= 1'b0;
 		else
             adffn <= dinA[0];
-            
-    always @( posedge clk, posedge dinA[2] )
+
+    always @( posedge clk )
 		if ( dinA[2] )
             dffe <= dinA[0];
             

architecture/synth_xilinx/top.v

@@ -35,7 +35,7 @@ module dffe
     initial begin
       q = 0;
     end
-	always @( posedge clk, posedge en )
+	always @( posedge clk )
 		if ( en )
 `ifndef BUG        
 			q <= d;

architecture/synth_xilinx_error/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

architecture/synth_xilinx_error/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

backends/Makefile

@@ -32,19 +32,27 @@ $(eval $(call template,write_btor_logic,write_btor write_btor_v write_btor_s))
 $(eval $(call template,write_btor_mem,write_btor_mem write_btor_mem_v write_btor_mem_s))
 $(eval $(call template,write_btor_pmux,write_btor_pmux))
 $(eval $(call template,write_btor_and_or,write_btor_and_or))
+$(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
 
 #write_edif
 $(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
 
 #write_firrtl
-$(eval $(call template,write_firrtl,write_firrtl ))
-# - issue #922
-#ERROR: Unclocked write port 0 on memory top.ram.
-#$(eval $(call template,write_firrtl_mem,write_firrtl_mem ))
+$(eval $(call template,write_firrtl,write_firrtl))
+#write_firrtl_mem_wr - issue #938
+#terminate called after throwing an instance of 'std::out_of_range'
+#  what():  dict::at()
+#run.sh: line 11:  9808 Aborted                 (core dumped)
+$(eval $(call template,write_firrtl_mem,write_firrtl_mem ))
+$(eval $(call template,write_firrtl_logic,write_firrtl ))
+$(eval $(call template,write_firrtl_reduce,write_firrtl ))
+$(eval $(call template,write_firrtl_shift,write_firrtl ))
+$(eval $(call template,write_firrtl_shiftx,write_firrtl ))
+$(eval $(call template,write_firrtl_paramod,write_firrtl))
 
 #write_ilang
 $(eval $(call template,write_ilang,write_ilang write_ilang_selected))
-$(eval $(call template,write_ilang_mem,write_ilang write_ilang_selected))
+$(eval $(call template,write_ilang_mem,write_ilang_mem))
 $(eval $(call template,write_ilang_mux,write_ilang write_ilang_selected))
 $(eval $(call template,write_ilang_fsm,write_ilang write_ilang_selected))
 $(eval $(call template,write_ilang_tri,write_ilang write_ilang_selected))
@@ -67,16 +75,18 @@ $(eval $(call template,write_smt2_mem,write_smt2 write_smt2_verbose write_smt2_s
 $(eval $(call template,write_smt2_fsm,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
 $(eval $(call template,write_smt2_init_assert,write_smt2_init_assert))
 $(eval $(call template,write_smt2_reduce,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
+$(eval $(call template,write_smt2_shiftx,write_smt2 write_smt2_synth write_smt2_verbose write_smt2_stbv write_smt2_stdt write_smt2_nomem write_smt2_wires write_smt2_tpl write_smt2_bv write_smt2_mem write_smt2_nobv))
 
 #write_smv
 $(eval $(call template,write_smv,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
-$(eval $(call template,write_smv_wide,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
-$(eval $(call template,write_smv_shift,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
+$(eval $(call template,write_smv_wide,write_smv write_smv_verbose write_smv_tpl))
+$(eval $(call template,write_smv_shift,write_smv_shift))
 $(eval $(call template,write_smv_fsm,write_smv write_smv_noproc write_smv_verbose write_smv_tpl))
 $(eval $(call template,write_smv_reduce,write_smv_noproc))
 $(eval $(call template,write_smv_logic,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
 $(eval $(call template,write_smv_init_assert,write_smv_init_assert))
 $(eval $(call template,write_smv_cmos4,write_smv_cmos4))
+$(eval $(call template,write_smv_shiftx,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
 
 #write_spice
 $(eval $(call template,write_spice,write_spice write_spice_top write_spice_big_endian write_spice_neg_i write_spice_pos_i write_spice_nc_prefix write_spice_inames ))
@@ -90,6 +100,7 @@ $(eval $(call template,write_verilog_tri,write_verilog write_verilog_nostr write
 $(eval $(call template,write_verilog_ffs,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
 $(eval $(call template,write_verilog_latch,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
 $(eval $(call template,write_verilog_concat,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
+$(eval $(call template,write_verilog_shiftx,write_verilog write_verilog_nostr write_verilog_siminit write_verilog_v ))
 
 
 

backends/common.v

+module assert_equal(input clk, input test, input pat);
+    always @(posedge clk)
+    begin
+        if (test != pat)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time);
+            $stop;
+        end
+    end
+endmodule 
+
 module assert_dff(input clk, input test, input pat);
     always @(posedge clk)
     begin
+        #1;
         if (test != pat)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time);
@@ -24,7 +36,7 @@ endmodule
 module assert_Z(input clk, input A);
     always @(posedge clk)
     begin
-        //#1;
+        #1;
         if (A === 1'bZ)
         begin
             $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);

backends/run.sh

 #!/bin/bash
 
-set -ex
+set -x
 test -d $1
 test -f scripts/$2.ys
 
@@ -8,17 +8,36 @@ rm -rf $1/work_$2
 mkdir $1/work_$2
 cd $1/work_$2
 
+touch .start
+
 yosys -ql yosys.log ../../scripts/$2.ys
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 sed -i 's/reg =/dummy =/' ./synth.v
-iverilog -o testbench  ../testbench.v synth.v ../../common.v ../../../../../techlibs/common/simcells.v ../../../../../techlibs/common/simlib.v
+
+if [ -f "../../../../../techlibs/common/simcells.v" ]; then
+    COMMON_PREFIX=../../../../../techlibs/common
+else
+    COMMON_PREFIX=/usr/local/share/yosys
+fi
+
+iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v
+if [ $? != 0 ] ; then
+    echo FAIL > ${1}_${2}.status
+    touch .stamp
+    exit 0
+fi
 
 if ! vvp -N testbench > testbench.log 2>&1; then
 	grep 'ERROR' testbench.log
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
-	echo fail > ${1}_${2}.status
+	echo FAIL > ${1}_${2}.status
 else
-	echo pass > ${1}_${2}.status
+	echo PASS > ${1}_${2}.status
 fi
 
 touch .stamp

backends/scripts/write_aiger.ys

 read_verilog -sv ../top.v
 aigmap
 write_aiger aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
 synth -top top
 write_verilog synth.v 

backends/scripts/write_aiger_B.ys

 read_verilog -sv ../top.v
 aigmap
 write_aiger -B aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
 synth -top top
 write_verilog synth.v 

backends/scripts/write_aiger_I.ys

 read_verilog -sv ../top.v
 aigmap
 write_aiger -I aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
 synth -top top
 write_verilog synth.v 

backends/scripts/write_aiger_O.ys

 read_verilog -sv ../top.v
 aigmap
 write_aiger -O aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
 synth -top top
 write_verilog synth.v 

backends/scripts/write_aiger_ascii.ys

 read_verilog -sv ../top.v
 aigmap
 write_aiger -ascii aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
 synth -top top
 write_verilog synth.v 

backends/scripts/write_aiger_map.ys

 read_verilog -sv ../top.v
 aigmap
 write_aiger -map a.map aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
 synth -top top
 write_verilog synth.v 

backends/scripts/write_aiger_miter.ys

@@ -2,4 +2,9 @@ read_verilog -sv ../top_clean.v
 synth -top top
 aigmap
 write_aiger -miter aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
+synth -top top
 write_verilog synth.v 

backends/scripts/write_aiger_symbols.ys

 read_verilog -sv ../top.v
 aigmap
 write_aiger -symbols aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
 synth -top top
 write_verilog synth.v 

backends/scripts/write_aiger_vmap.ys

 read_verilog -sv ../top.v
 aigmap
 write_aiger -vmap a.map aiger.aiger
+design -reset
+read_verilog -sv ../top_clean.v
+aigmap
+write_aiger aiger.aiger
 synth -top top
 write_verilog synth.v 

backends/scripts/write_firrtl.ys

 read_verilog ../top.v
 proc
 write_firrtl firrtl.firrtl
-write_verilog synth.v 
+synth
+write_firrtl firrtl2.firrtl
+write_verilog synth.v

backends/scripts/write_firrtl_mem.ys

 read_verilog ../top.v
-memory_collect
 proc
+memory_dff -nordff
+memory_collect
+opt_reduce
+clean
 write_firrtl firrtl.firrtl
-write_verilog synth.v 
+write_verilog synth.v

backends/scripts/write_firrtl_mem_wr.ys

+read_verilog ../top.v
+proc
+memory_dff -nordff
+opt_reduce
+clean
+write_firrtl firrtl.firrtl
+write_verilog synth.v

backends/scripts/write_ilang.ys

@@ -4,4 +4,5 @@ proc
 dump -o file.il
 write_ilang ilang.ilang
 dump -n -o file1.il
+synth
 write_verilog synth.v

backends/scripts/write_ilang_mem.ys

+read_verilog ../top.v
+proc
+memory
+dump -o file.il
+write_ilang ilang.ilang
+dump -n -o file1.il
+write_verilog synth.v

backends/scripts/write_smt2.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_bv.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 -bv smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_mem.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 -mem smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_mem_memtest.ys

 read_verilog ../top.v
-memory_collect
 proc
+memory
 write_smt2 -mem smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_memtest.ys

 read_verilog ../top.v
-memory_collect
 proc
+memory
 write_smt2 smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_nomem.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 -nomem smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_stbv.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 -stbv smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_stbv_memtest.ys

 read_verilog ../top.v
-memory_collect
 proc
+memory
 write_smt2 -stbv smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_stdt.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 -stdt smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_tpl.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 -tpl ../top.tpl smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_verbose.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 -verbose smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smt2_wires.ys

 read_verilog ../top.v
 proc
+memory
 write_smt2 -wires smt2.smt2
 write_verilog synth.v 

backends/scripts/write_smv_shift.ys

+read_verilog ../top.v
+proc
+write_smv smv.smv
+design -reset
+read_verilog ../top_clean.v
+proc
+write_smv smv.smv
+write_verilog synth.v

backends/write_aiger/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_blif/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_blif/top.v

@@ -45,4 +45,7 @@ endmodule
  input clk;
 
  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
 endmodule

backends/write_btor/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_div_mod/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_logic/testbench.v

@@ -5,8 +5,8 @@ module testbench;
 	reg patt_carry_out = 0;
 	reg patt_out1 = 0;
 	reg patt_carry_out1 = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_shift/testbench.v

@@ -3,8 +3,8 @@ module testbench;
 
 	reg patt_out = 0;
 	reg patt_carry_out = 0;
-	wire out = 0;
-    wire carryout = 0;
+	wire out;
+    wire carryout;
 
     initial begin
         // $dumpfile("testbench.vcd");

backends/write_btor_shiftx/testbench.v

+module testbench;
+    reg [4:0] in;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    wire out,y;
+
+    top uut (
+	.a(in),
+	.y(out)
+	);
+
+	integer i, j;
+	reg [31:0] lut;
+
+	initial begin
+		for (i = 0; i < 32; i = i+1) begin
+			lut[i] = i > 1;
+			for (j = 2; j*j <= i; j = j+1)
+				if (i % j == 0)
+					lut[i] = 0;
+		end
+	end
+
+	assign y = lut[in];
+
+	assert_comb out_test(.A(y), .B(out));
+
+endmodule

backends/write_btor_shiftx/top.v

+
+// VERIFIC-SKIP
+
+module top(a, y);
+
+input signed [4:0] a;
+output signed y;
+
+integer i = 0, j = 0;
+reg [31:0] lut;
+
+initial begin
+	for (i = 0; i < 32; i = i+1) begin
+		lut[i] = i > 1;
+		for (j = 2; j*j <= i; j = j+1)
+			if (i % j == 0)
+				lut[i] = 0;
+	end
+end
+
+assign y = lut[a];
+
+endmodule

backends/write_btor_shiftx/top_clean.v

+
+// VERIFIC-SKIP
+
+module top(a, y);
+
+input [4:0] a;
+output y;
+
+integer i = 0, j = 0;
+reg [31:0] lut;
+
+initial begin
+	for (i = 0; i < 32; i = i+1) begin
+		lut[i] = i > 1;
+		for (j = 2; j*j <= i; j = j+1)
+			if (i % j == 0)
+				lut[i] = 0;
+	end
+end
+
+assign y = lut[a];
+
+endmodule