fix asserts

architecture/synth_xilinx/synth_xilinx_nodsp.ys

@@ -17,14 +17,14 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -nodsp # equivalency ch
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 stat
-select -assert-count 15 t:LUT2
-select -assert-count 3 t:LUT3
+select -assert-count 14 t:LUT2
+select -assert-count 4 t:LUT3
 select -assert-count 4 t:LUT4
-select -assert-count 5 t:LUT5
-select -assert-count 45 t:LUT6
+select -assert-count 4 t:LUT5
+select -assert-count 43 t:LUT6
 select -assert-count 11 t:MUXCY
-select -assert-count 9 t:MUXF7
-select -assert-count 3 t:MUXF8
+select -assert-count 7 t:MUXF7
+select -assert-count 2 t:MUXF8
 select -assert-count 12 t:XORCY
 select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D