Commit 60ac790e by SergeyDegtyar

Fix tests in 'regression' for the current Yosys revision.

parent 2da46f4b
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
module top(b);
module top(b,c);
input b;
output c;
assign c = b;
endmodule
......@@ -13,10 +13,11 @@ module testbench;
$display("OKAY");
end
wire c;
top uut (
.b (clk )
.b (clk ),
.c (c)
);
endmodule
parameter X = 2;
module top(b);
module top(b,c);
input b;
output c;
parameter Y = 3;
assign c = b;
endmodule
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