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yosys-tests
Commit 2da46f4b by SergeyDegtyar
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Revert "Add new tests to 'regression'" 

This reverts commit 3682484e.
parent e0161763
Showing with 6 additions and 208 deletions
regression/Makefile
......@@ -29,8 +29,8 @@ $(eval $(call template,issue_00041,issue_00041))
#issue_00059
$(eval $(call template,issue_00059,issue_00059))
#issue_00065 - 27_04 test hangs up
#$(eval $(call template,issue_00065,issue_00065))
#issue_00065
$(eval $(call template,issue_00065,issue_00065))
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
......@@ -297,7 +297,7 @@ $(eval $(call template,issue_00763,issue_00763))
#issue_00767
$(eval $(call template,issue_00767,issue_00767))
#issue_00774 -takes too much time
#issue_00774
#$(eval $(call template,issue_00774,issue_00774))
#issue_00781
......@@ -336,29 +336,10 @@ $(eval $(call template,issue_00857,issue_00857))
#issue_00862
$(eval $(call template,issue_00862,issue_00862))
#issue_00865
#issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
$(eval $(call template,issue_00865,issue_00865))
#issue_00867
$(eval $(call template,issue_00867,issue_00867))
#issue_00870
$(eval $(call template,issue_00870,issue_00870))
#issue_00873
$(eval $(call template,issue_00873,issue_00873))
#issue_00888
$(eval $(call template,issue_00888,issue_00888))
#pr_00896
$(eval $(call template,pr_00896,pr_00896))
#issue_00922
$(eval $(call template,issue_00922,issue_00922))
#issue_00931
$(eval $(call template,issue_00931,issue_00931))
.PHONY: all clean
regression/issue_00870/top.v deleted 100644 → 0
module mux1( select, d, q );
input select;
input[1:0] d;
output q;
wire q;
wire select;
wire[1:0] d;
assign q = d[select];
endmodule
module top(select, d, q);
input[1:0] select;
input[1:0] d;
output q;
wire q;
wire[1:0] select;
wire[1:0] d;
wire[1:0] q_tmp;
mux1 m1(
.select(select[0]),
.d(d),
.q(q_tmp[0])
);
mux1 m2(
.select(select[1]),
.d(d),
.q(q_tmp[1])
);
mux1 m3(
.select(select[0]),
.d(q_tmp),
.q(q)
);
endmodule
regression/issue_00873/top.v deleted 100644 → 0
module template (input clk, input d, output reg q);
parameter neg_clk = 0;
initial q = 1'b1;
generate
if (neg_clk) begin
always @(negedge clk) q <= d;
end
else begin
always @(posedge clk) q <= d;
end
endgenerate
endmodule
module top(input clk, input d, output [1:0] q);
template #(.neg_clk(1)) neg_clk(clk, d, q[0]);
template #(.neg_clk(0)) pos_clk(clk, d, q[1]);
endmodule
regression/issue_00888/top.v deleted 100644 → 0
module top (CLK, CE, SEL, SI, DO);
parameter SELWIDTH = 1;
parameter DATAWIDTH = 2;
input CLK, CE;
input [DATAWIDTH-1:0] SI;
input [SELWIDTH-1:0] SEL;
output [DATAWIDTH-1:0] DO;
localparam DATADEPTH = 2**SELWIDTH;
reg [0:DATADEPTH-1] data1 [DATAWIDTH-1:0];
reg [DATADEPTH-1:0] data2 [DATAWIDTH-1:0];
generate
genvar i;
for (i = 0; i < DATAWIDTH; i=i+1) begin
always @(posedge CLK)
begin
if (CE == 1'b1) begin
`ifdef BROKEN
data1[i] <= {SI[i], data1[i][0:DATADEPTH-2]};
`else
data2[i] <= {data2[i][DATADEPTH-2:0], SI[i]};
`endif
end
end
`ifdef BROKEN
assign DO[i] = data1[i][SEL];
`else
assign DO[i] = data2[i][SEL];
`endif
end
endgenerate
endmodule
regression/issue_00922/top.v deleted 100644 → 0
module top
(
input [7:0] data_a, data_b,
input [6:1] addr_a, addr_b,
input we_a, we_b, re_a, re_b, clka, clkb,
output reg [7:0] q_a, q_b
);
// Declare the RAM variable
reg [7:0] ram[63:0];
/*initial begin
q_a <= 8'h00;
q_b <= 8'd0;
end*/
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
end
endmodule
regression/issue_00931/top.v deleted 100644 → 0
module top (
input [1:0] S,
input [7:0] A, B, C, D,
output reg [7:0] Y
);
always @* begin
case (S)
2'b00: Y <= A;
2'b01: Y <= B;
2'b10: Y <= C;
2'b11: Y <= D;
endcase
end
endmodule
regression/run.sh
......@@ -73,13 +73,7 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00835" ] ||\
[ "$1" = "issue_00857" ] ||\
[ "$1" = "issue_00862" ] ||\
[ "$1" = "issue_00865" ] ||\
[ "$1" = "issue_00867" ] ||\
[ "$1" = "issue_00870" ] ||\
[ "$1" = "issue_00873" ] ||\
[ "$1" = "issue_00888" ] ||\
[ "$1" = "issue_00922" ] ||\
[ "$1" = "issue_00931" ]; then
[ "$1" = "issue_00865" ]; then
expected_string=""
expected="1"
......@@ -97,8 +91,7 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00689" ] ||\
[ "$1" = "issue_00708" ] ||\
[ "$1" = "issue_00826" ] ||\
[ "$1" = "issue_00862" ] ||\
[ "$1" = "issue_00870" ]; then
[ "$1" = "issue_00862" ]; then
expected_string="Successfully finished Verilog frontend"
elif [ "$1" = "issue_00655" ]; then
expected_string="Executing EDIF backend"
......@@ -124,18 +117,6 @@ elif [ "$1" = "issue_00502" ] ||\
expected_string="_DFF_P_ 1"
elif [ "$1" = "issue_00865" ]; then
expected_string="FDRE 14"
elif [ "$1" = "issue_00867" ]; then
expected_string="RAMB36E1 1"
elif [ "$1" = "issue_00873" ]; then
expected_string="has an unprocessed 'init' attribute."
expected="0"
elif [ "$1" = "issue_00888" ]; then
expected_string="FDRE 4"
elif [ "$1" = "issue_00922" ]; then
expected_string="ERROR: Unclocked write port 0 on memory top.ram."
expected="0"
elif [ "$1" = "issue_00931" ]; then
expected_string="Number of cells: 5"
fi
yosys -ql yosys.log ../../scripts/$2.ys;
......
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