Merge pull request #59 from SergeyDegtyar/master

Add new tests for passes/techmap, abc9, test_cell, synth -abc9; New tests to 'architecture'.

architecture/Makefile

@@ -38,20 +38,21 @@ $(eval $(call template,synth_coolrunner2_error,synth_coolrunner2_fully_selected)
 $(eval $(call template,synth_easic_error,synth_easic_fully_selected))
 
 #ecp5
-$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
-$(eval $(call template,synth_ecp5_wide_ffs,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit))
+$(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit synth_ecp5_abc9 synth_ecp5_abc9_nowidelut))
+$(eval $(call template,synth_ecp5_wide_ffs,synth_ecp5 synth_ecp5_top synth_ecp5_blif synth_ecp5_edif synth_ecp5_json synth_ecp5_run synth_ecp5_flatten synth_ecp5_noflatten synth_ecp5_retime synth_ecp5_noccu2 synth_ecp5_nodffe synth_ecp5_nobram synth_ecp5_nodram synth_ecp5_nomux synth_ecp5_abc2 synth_ecp5_vpr ecp5_ffinit  synth_ecp5_abc9 synth_ecp5_abc9_nowidelut))
 $(eval $(call template,synth_ecp5_error,synth_ecp5_fully_selected))
 
 #gowin
-$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten ))
-$(eval $(call template,synth_gowin_mem,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten ))
+$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe ))
+$(eval $(call template,synth_gowin_mem,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe ))
 $(eval $(call template,synth_gowin_error,synth_gowin_fully_selected ))
 
 #ice40
-$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
-$(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
-$(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc))
-$(eval $(call template,synth_ice40_error,synth_ice40_fully_selected))
+$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
+$(eval $(call template,synth_ice40_mem,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_abc9 synth_ice40_unlut synth_ice40_opt))
+$(eval $(call template,synth_ice40_wide_ffs,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
+$(eval $(call template,synth_ice40_fulladder,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt))
+$(eval $(call template,synth_ice40_error,synth_ice40_fully_selected synth_ice40_abc9_retime synth_ice40_device_unknown))
 
 #intel
 $(eval $(call template,synth_intel,synth_intel synth_intel_top synth_intel_vqm synth_intel_vpr synth_intel_run synth_intel_noflatten synth_intel_retime synth_intel_iopads synth_intel_nobram synth_intel_max10 ))
@@ -67,8 +68,8 @@ $(eval $(call template,synth_sf2,synth_sf2 synth_sf2_top synth_sf2_edif synth_sf
 $(eval $(call template,synth_sf2_error,synth_sf2_fully_selected ))
 
 #xilinx
-$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl))
-$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch ))
+$(eval $(call template,synth_xilinx,synth_xilinx synth_xilinx_top synth_xilinx_blif synth_xilinx_edif synth_xilinx_run synth_xilinx_flatten synth_xilinx_retime synth_xilinx_vpr synth_xilinx_arch_xcup synth_xilinx_arch_xcu synth_xilinx_arch_xc7 synth_xilinx_arch_xc6s synth_xilinx_nobram synth_xilinx_nodram synth_xilinx_nosrl synth_xilinx_widemux synth_xilinx_nowidelut synth_xilinx_nocarry synth_xilinx_arch_xc6s_abc9 synth_xilinx_widemux_9 synth_xilinx_widemux_2 synth_xilinx_widemux_3 synth_xilinx_nowidelut_abc9))
+$(eval $(call template,synth_xilinx_error,synth_xilinx_fully_selected synth_xilinx_invalid_arch synth_xilinx_abc9_retime synth_xilinx_widemux_1))
 ifeq ($(ENABLE_HEAVY_TESTS),1)
 $(eval $(call template,synth_xilinx_srl,synth_xilinx_srl))
 $(eval $(call template,synth_xilinx_mux,synth_xilinx_mux))
@@ -77,6 +78,7 @@ endif
 #greenpak4
 $(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
 $(eval $(call template,synth_greenpak4_wide_ffs,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
+$(eval $(call template,synth_greenpak4_dffs_r,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140))
 $(eval $(call template,synth_greenpak4_error,synth_greenpak4_fully_selected synth_greenpak4_invalid_part))
 
 .PHONY: all clean

architecture/run.sh

@@ -22,6 +22,14 @@ if echo "$1" | grep ".*_error"; then
 		expected_string="ERROR: Invalid or no family specified:"
 	elif [ "$2" = "synth_xilinx_invalid_arch" ]; then
 		expected_string="ERROR: Invalid Xilinx -family setting: "
+	elif [ "$2" = "synth_xilinx_widemux_1" ]; then
+		expected_string="ERROR: -widemux value must be 0 or >= 2."
+	elif [ "$2" = "synth_xilinx_abc9_retime" ]; then
+		expected_string="ERROR: -retime option not currently compatible with -abc9!"
+	elif [ "$2" = "synth_ice40_abc9_retime" ]; then
+		expected_string="ERROR: -retime option not currently compatible with -abc9!"
+	elif [ "$2" = "synth_ice40_device_unknown" ]; then
+		expected_string="ERROR: Invalid or no device specified: "
 	fi
 
 	if yosys -ql yosys.log ../../scripts/$2.ys; then
@@ -87,6 +95,8 @@ else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 	elif [ "$1" = "synth_ice40_wide_ffs" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
+	elif [ "$1" = "synth_ice40_fulladder" ]; then
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/ice40/cells_sim.v
 	elif [ "$1" = "synth_intel" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/intel/max10/cells_sim.v
 	elif [ "$1" = "synth_intel_a10gx" ]; then
@@ -107,6 +117,8 @@ else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
 	elif [ "$1" = "synth_greenpak4_wide_ffs" ]; then
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
+	elif [ "$1" = "synth_greenpak4_dffs_r" ]; then
+		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $TECHLIBS_PREFIX/greenpak4/cells_sim_digital.v
 	else
 		iverilog -o testbench  ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v
 	fi

architecture/scripts/synth_ecp5_abc9.ys

+read_verilog ../top.v
+synth_ecp5 -abc9
+write_verilog synth.v

architecture/scripts/synth_ecp5_abc9_nowidelut.ys

+read_verilog ../top.v
+synth_ecp5 -abc9 -nowidelut
+write_verilog synth.v

architecture/scripts/synth_gowin_nodffe.ys

+read_verilog ../top.v
+synth_gowin -nodffe
+write_verilog synth.v

architecture/scripts/synth_gowin_nodram.ys

+read_verilog ../top.v
+synth_gowin -nodram
+write_verilog synth.v

architecture/scripts/synth_ice40_abc9.ys

+read_verilog ../top.v
+synth_ice40 -abc9
+ice40_unlut
+ice40_opt
+write_verilog synth.v

architecture/scripts/synth_ice40_abc9_retime.ys

+read_verilog ../top.v
+synth_ice40 -abc9 -retime
+write_verilog synth.v

architecture/scripts/synth_ice40_device_hx.ys

+read_verilog ../top.v
+synth_ice40 -device hx
+write_verilog synth.v

architecture/scripts/synth_ice40_device_lp.ys

+read_verilog ../top.v
+synth_ice40 -device lp
+write_verilog synth.v

architecture/scripts/synth_ice40_device_u.ys

+read_verilog ../top.v
+synth_ice40 -device u
+write_verilog synth.v

architecture/scripts/synth_ice40_device_unknown.ys

+read_verilog ../top.v
+synth_ice40 -device unknown
+write_verilog synth.v

architecture/scripts/synth_ice40_opt.ys

+read_verilog ../top.v
+synth_ice40
+ice40_opt
+write_verilog synth.v

architecture/scripts/synth_ice40_unlut.ys

+read_verilog ../top.v
+synth_ice40
+ice40_unlut
+write_verilog synth.v

architecture/scripts/synth_xilinx_abc9.ys

+read_verilog ../top.v
+synth_xilinx -abc9
+write_verilog synth.v

architecture/scripts/synth_xilinx_abc9_retime.ys

+read_verilog ../top.v
+synth_xilinx -abc9 -retime
+write_verilog synth.v

architecture/scripts/synth_xilinx_arch_xc6s_abc9.ys

+read_verilog ../top.v
+synth_xilinx -arch xc6s -abc9
+write_verilog synth.v

architecture/scripts/synth_xilinx_nocarry.ys

+read_verilog ../top.v
+synth_xilinx -nocarry
+write_verilog synth.v

architecture/scripts/synth_xilinx_nowidelut.ys

+read_verilog ../top.v
+synth_xilinx -nowidelut
+write_verilog synth.v

architecture/scripts/synth_xilinx_nowidelut_abc9.ys

+read_verilog ../top.v
+synth_xilinx -nowidelut -abc9
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux.ys

+read_verilog ../top.v
+synth_xilinx -widemux 5
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux_1.ys

+read_verilog ../top.v
+synth_xilinx -widemux 1
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux_2.ys

+read_verilog ../top.v
+synth_xilinx -widemux 2
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux_3.ys

+read_verilog ../top.v
+synth_xilinx -widemux 3
+write_verilog synth.v

architecture/scripts/synth_xilinx_widemux_9.ys

+read_verilog ../top.v
+synth_xilinx -widemux 9
+write_verilog synth.v

architecture/synth_greenpak4_dffs_r/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1;
+	reg dffs,dffr = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk, negedge dinA[1] )
+		if ( !dinA[1] )
+			dffs <= 1'b1;
+		else
+            dffs <= dinA[0];
+
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			dffr <= 1'b0;
+		else
+            dffr <= dinA[0];
+
+	assert_dff dffs_test(.clk(clk), .test(doutB), .pat(dffs));
+    assert_dff dffr_test(.clk(clk), .test(doutB1), .pat(dffr));
+
+endmodule

architecture/synth_greenpak4_dffs_r/top.v

+module dffs
+    ( input d, clk, pre, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge pre )
+		if ( !pre )
+`ifndef BUG
+			q <= 1'b1;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffr
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1
+);
+
+dffs u_dffs (
+        .clk (clk ),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+dffr u_dffr (
+        .clk (clk ),
+        .clr (clr ),
+        .d (a ),
+        .q (b1 )
+    );
+
+endmodule

architecture/synth_ice40_fulladder/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+	
+	assign {patt_carry_out,patt_out} =  in[2] + in[1] + in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

architecture/synth_ice40_fulladder/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/Makefile

@@ -59,6 +59,9 @@ $(eval $(call template,write_firrtl_reduce,write_firrtl ))
 $(eval $(call template,write_firrtl_shift,write_firrtl ))
 $(eval $(call template,write_firrtl_shiftx,write_firrtl ))
 $(eval $(call template,write_firrtl_paramod,write_firrtl))
+$(eval $(call template,write_firrtl_mul,write_firrtl))
+$(eval $(call template,write_firrtl_sub,write_firrtl))
+$(eval $(call template,write_firrtl_pow,write_firrtl))
 $(eval $(call template,write_firrtl_error, write_firrtl_fully_selected write_firrtl_negative_edge_ff write_firrtl_inout_port write_firrtl_unclocked_write_port write_firrtl_complex_write_enable ))
 
 #write_ilang

backends/write_firrtl_mul/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+	assign patt_carry_out =  in[2] / in[1];
+	assign patt_out =  in[2] * in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	//assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_firrtl_mul/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign cout =  cin / y;
+assign A =  cin * x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_firrtl_pow/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+	//assign patt_carry_out =  in[2] ** in[1];
+	assign patt_out =  in[2] * in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	//assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_firrtl_pow/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+ wire pow,p,n;
+
+assign pow = 2 ** y;
+
+assign p =  +x;
+assign n =  -x;
+assign A =  cin * x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

backends/write_firrtl_sub/testbench.v

+module testbench;
+    reg [2:0] in;
+
+	wire patt_out,out;
+	wire patt_carry_out,carryout;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(out),
+	.cout(carryout)
+	);
+
+	assign patt_carry_out =  in[2] % in[1];
+	assign patt_out =  in[2] - in[0];
+
+	assert_comb out_test(.A(patt_out), .B(out));
+	//assert_comb carry_test(.A(patt_carry_out), .B(carryout));
+
+endmodule

backends/write_firrtl_sub/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign cout =  cin % y;
+assign A =  cin - x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc/Makefile

@@ -23,7 +23,7 @@ $(eval $(call template,test_abcloop,test_abcloop test_abcloop_n test_abcloop_s )
 #test_cell
 #test_cell_map - takes a lot of time
 # test_cell_mux, test_cell_pmux - is not supported
-$(eval $(call template,test_cell,test_cell test_cell_aigmap test_cell_const test_cell_edges test_cell_f  test_cell_div test_cell_muxdiv test_cell_n test_cell_noeval test_cell_nosat test_cell_s test_cell_script test_cell_simlib test_cell_v test_cell_vlog test_cell_w test_cell_alu test_cell_sop test_cell_lut test_cell_macc test_cell_lcu test_cell_fa))
+$(eval $(call template,test_cell,test_cell test_cell_aigmap test_cell_const test_cell_edges test_cell_f  test_cell_div test_cell_muxdiv test_cell_n test_cell_noeval test_cell_nosat test_cell_s test_cell_script test_cell_simlib test_cell_v test_cell_vlog test_cell_w test_cell_alu test_cell_sop test_cell_lut test_cell_macc test_cell_lcu test_cell_fa test_cell_wo_synth test_cell_map))
 $(eval $(call template,test_cell_error, test_cell_failed_to_open test_cell_unexpected_opt test_cell_cell_type_not_supported test_cell_no_cell_t_specified test_cell_dont_spec_cell_type_with_f ))
 
 #torder
@@ -208,9 +208,9 @@ $(eval $(call template,tee_error, tee_o_cant_create_file tee_a_cant_create_file
 $(eval $(call template,test_autotb, test_autotb test_autotb_file test_autotb_n test_autotb_seed))
 
 #abc
-$(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
-$(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
-$(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
+$(eval $(call template,abc, abc_D abc_g_aig abc_g_cmos2 abc_g_cmos abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
+$(eval $(call template,abc_dff, abc_D abc_g_aig abc_g_cmos2 abc_g_cmos abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
+$(eval $(call template,abc_mux, abc_D abc_g_aig abc_g_cmos2 abc_g_cmos abc_g_simple abc_mux16 abc_mux4 abc_mux8 abc_S abc_dff abc_constr_liberty))
 $(eval $(call template,abc_error, abc_cannot_open abc_constr_no_liberty abc_lut_liberty abc_unsup_gate_type abc_inv_luts_synt  abc_return_code abc_clk_domain_not_found abc_script_o abc_script_top))
 
 #hilomap
@@ -269,7 +269,11 @@ $(eval $(call template,script, script script_from_to script_scriptwire ))
 $(eval $(call template,tcl, tcl ))
 
 #abc9
-$(eval $(call template,abc9, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D ))
+$(eval $(call template,abc9, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D abc9_W abc9_wo_proc abc9_wo_synth abc9_box abc9_script))
+$(eval $(call template,abc9_dff, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D abc9_W abc9_wo_proc abc9_wo_synth))
+$(eval $(call template,abc9_mux, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D abc9_W abc9_wo_proc abc9_wo_synth))
+$(eval $(call template,abc9_mem, abc9_markgroups abc9_showtmp abc9_nocleanup abc9_luts abc9_lut abc9_fast abc9_D abc9_W abc9_wo_proc abc9_wo_synth))
+$(eval $(call template,abc9_error, abc9_invalid_luts_syntax abc9_cant_open_output_file))
 
 
 .PHONY: all clean

misc/abc9_dff/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

misc/abc9_error/top.v

+(* black_box *) module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output A,
+ output cout
+ );
+
+`ifndef BUG
+assign {cout,A} =  cin + y + x;
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc/abc9_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

misc/abc9_mux/top.v

+module top (
+input [7:0] S,
+input [255:0] D,
+output M256
+);
+
+assign M256 = D[S];
+
+endmodule

misc/run.sh

@@ -378,6 +378,10 @@ if echo "$1" | grep ".*_error"; then
 	elif [ "$2" = "write_file_missing_name" ] || \
 		 [ "$2" = "write_file_a_missing_name" ]; then
  		expected_string="ERROR: Missing output filename."
+	elif [ "$2" = "abc9_invalid_luts_syntax" ]; then
+ 		expected_string="ERROR: Invalid -luts syntax."
+	elif [ "$2" = "abc9_cant_open_output_file" ]; then
+ 		expected_string="ERROR: Can't open ABC output file"
 	fi
 
 

misc/scripts/abc9_W.ys

+read_verilog ../top.v
+proc
+dff2dffe
+synth -top top
+tee -o result.log abc9 -W -lut 2

misc/scripts/abc9_box.ys

+tee -o result.log abc9 -box box.txt -lut 2

misc/scripts/abc9_cant_open_output_file.ys

+read_verilog ../top.v
+tee -o result.log abc9 -luts uu

misc/scripts/abc9_invalid_luts_syntax.ys

+read_verilog ../top.v
+tee -o result.log abc9 -luts 2:2:2:/2

misc/scripts/abc9_script.ys

+tee -o result.log abc9 -script box.txt -lut 2

misc/scripts/abc9_wo_proc.ys

+read_verilog ../top.v
+tee -o result.log abc9 -lut 2

misc/scripts/abc9_wo_synth.ys

+read_verilog ../top.v
+proc
+tee -o result.log abc9 -lut 2

misc/scripts/abc_g_cmos.ys

+read_verilog ../top.v
+synth -top top
+tee -o result.log abc -g cmos

misc/scripts/test_cell_map.ys

 read_verilog ../top.v
 synth -top top
-tee -o result.log test_cell -n 2 -map ../simlib.v $add
+tee -o result.log test_cell -n 2 -map +/techmap.v $add

misc/scripts/test_cell_wo_synth.ys

+read_verilog ../top.v
+proc
+tee -o result.log test_cell $add

simple/Makefile

@@ -64,7 +64,7 @@ $(eval $(call template,fsm, fsm))
 $(eval $(call template,fsm_opt, fsm))
 
 #Extract full and half adders
-$(eval $(call template,full_adder,full_adder half_adder))
+$(eval $(call template,full_adder,full_adder half_adder full_adder_d full_adder_b full_adder_wo_opt))
 
 #Extract reduce
 $(eval $(call template,reduce,reduce reduce_allow_off_chain))
@@ -84,7 +84,7 @@ $(eval $(call template,clk2fflogic_latch,clk2fflogic))
 $(eval $(call template,clk2fflogic_mem,clk2fflogic_mem))
 
 #muxcover
-$(eval $(call template,muxcover,muxcover muxcover_nodecode muxcover_mux4 muxcover_mux4_nodecode muxcover_mux16 muxcover_mux16_nodecode muxcover_4_8_16_nodecode))
+$(eval $(call template,muxcover,muxcover muxcover_nodecode muxcover_mux4 muxcover_mux4_nodecode muxcover_mux16 muxcover_mux16_nodecode muxcover_4_8_16_nodecode muxcover_mux2 muxcover_dmux))
 $(eval $(call template,muxcover_mux8,muxcover_mux8 muxcover_mux8_nodecode))
 
 #aigmap
@@ -143,7 +143,7 @@ $(eval $(call template,flowmap_latch,flowmap flowmap_cells flowmap_debug_relax f
 $(eval $(call template,flowmap_mem,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
 
 #iopadmap
-$(eval $(call template,iopadmap,iopadmap))
+$(eval $(call template,iopadmap,iopadmap iopadmap_dont_map))
 
 #tribuf
 $(eval $(call template,tribuf,tribuf tribuf_top tribuf_merge_top))
@@ -224,8 +224,15 @@ $(eval $(call template, prep, prep prep_top prep_auto_top prep_flatten prep_ifx
 $(eval $(call template_error, prep_error, prep_error))
 
 #synth
-$(eval $(call template, synth, synth synth_top synth_auto_top synth_encfile synth_run synth_run_full synth_flatten synth_lut synth_nofsm synth_noabc synth_noabc_lut synth_noalumacc synth_nordff synth_noshare))
-$(eval $(call template_error, synth_error, synth_error))
+$(eval $(call template, synth, synth synth_top synth_auto_top synth_encfile synth_run synth_run_full synth_flatten synth_lut synth_nofsm synth_noabc synth_noabc_lut synth_noalumacc synth_nordff synth_noshare synth_abc9))
+$(eval $(call template_error, synth_error, synth_error synth_abc9_no_lut))
 
+#simplemap
+$(eval $(call template, simplemap, simplemap simplemap_top simplemap_slice_concat))
+$(eval $(call template, simplemap_reduce, simplemap simplemap_top simplemap_slice_concat))
+$(eval $(call template, simplemap_mem_slice_concat, simplemap simplemap_top simplemap_slice_concat))
+
+#techmap
+$(eval $(call template, techmap, techmap techmap_wb techmap_autoproc techmap_recursive techmap_extern techmap_assert techmap_i techmap_d techmap_max_iter techmap_map))
 
 .PHONY: all clean

simple/run.sh

@@ -68,6 +68,8 @@ if echo "$1" | grep ".*_error"; then
 		expected_string="ERROR: More than one module selected:"
 	elif [ "$2" = "synth_error" ]; then
 		expected_string="ERROR: This command only operates on fully selected designs!"
+	elif [ "$2" = "synth_abc9_no_lut" ]; then
+		expected_string="ERROR: ABC9 flow only supported for FPGA synthesis (using '-lut' option)"
 	elif [ "$2" = "zinit_failed_to_handle" ]; then
 		expected_string="ERROR: Failed to handle init bit"
 	fi

simple/scripts/full_adder_b.ys

+read_verilog ../top.v
+synth -top top
+extract_fa -fa -b 12 top
+tee -o result.log dump
+synth -top top
+write_verilog synth.v

simple/scripts/full_adder_d.ys

+read_verilog ../top.v
+synth -top top
+extract_fa -fa -d 6 top
+tee -o result.log dump
+synth -top top
+write_verilog synth.v

simple/scripts/full_adder_wo_opt.ys

+read_verilog ../top.v
+synth -top top
+extract_fa
+tee -o result.log dump
+synth -top top
+write_verilog synth.v

simple/scripts/iopadmap_dont_map.ys

+read_verilog ../top.v
+proc
+iopadmap -widthparam wp
+iopadmap -nameparam np
+iopadmap -bits
+iopadmap -inpad IBUF O:I
+iopadmap -outpad IOBUFE O:IO
+iopadmap -inoutpad IOBUFE O:IO
+iopadmap -toutpad IOBUFE O:IO
+iopadmap -tinoutpad IOBUFE O:IO
+tee -o result.log dump
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v

simple/scripts/muxcover_dmux.ys

+read_verilog ../top.v
+synth -top top
+muxcover -dmux=3
+tee -o result.log dump
+write_verilog synth.v

simple/scripts/muxcover_mux2.ys

+read_verilog ../top.v
+synth -top top
+muxcover -mux2=336
+tee -o result.log dump
+write_verilog synth.v

simple/scripts/simplemap.ys

+read_verilog ../top.v
+prep
+simplemap
+synth
+write_verilog synth.v

simple/scripts/simplemap_slice_concat.ys

+read_verilog ../top.v
+synth
+splice
+simplemap top
+synth
+write_verilog synth.v

simple/scripts/simplemap_top.ys

+read_verilog ../top.v
+prep
+dff2dffe
+simplemap top
+synth
+write_verilog synth.v

simple/scripts/synth_abc9.ys

+read_verilog ../top.v
+synth -abc9 -lut 5
+write_verilog synth.v

simple/scripts/synth_abc9_no_lut.ys

+read_verilog ../top.v
+synth -abc9
+write_verilog synth.v

simple/scripts/techmap.ys

+read_verilog ../top.v
+proc
+techmap
+synth
+write_verilog synth.v

simple/scripts/techmap_assert.ys

+read_verilog ../top.v
+proc
+dff2dffe
+techmap -assert -map +/techmap.v +/simlib.v
+synth
+write_verilog synth.v

simple/scripts/techmap_autoproc.ys

+read_verilog ../top.v
+techmap -autoproc
+write_verilog synth.v

simple/scripts/techmap_d.ys

+read_verilog ../top.v
+proc
+techmap -D U
+synth
+write_verilog synth.v

simple/scripts/techmap_extern.ys

+read_verilog ../top.v
+proc
+techmap -extern
+synth
+write_verilog synth.v

simple/scripts/techmap_i.ys

+read_verilog ../top.v
+proc
+techmap -I techmap
+synth
+write_verilog synth.v

simple/scripts/techmap_map.ys

+read_verilog ../top.v
+proc
+techmap -map +/techmap.v
+synth
+write_verilog synth.v

simple/scripts/techmap_max_iter.ys

+read_verilog ../top.v
+proc
+techmap -max_iter 2
+synth
+write_verilog synth.v

simple/scripts/techmap_recursive.ys

+read_verilog ../top.v
+proc
+techmap -recursive
+synth
+write_verilog synth.v

simple/scripts/techmap_wb.ys

+read_verilog ../top.v
+techmap -wb
+write_verilog synth.v

simple/simplemap/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+	
+	always @( posedge clk, posedge dinA[1], posedge dinA[2] )
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+    
+    always @( negedge clk, negedge dinA[1], negedge dinA[2] )
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+            
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+            
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+            
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));    
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+    
+endmodule

simple/simplemap/top.v

+module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+`ifndef BUG        
+			q <= d;
+`else        
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge pre, posedge clr )
+		if ( clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk, negedge pre, negedge clr )
+		if ( !clr )
+`ifndef BUG        
+			q <= 1'b0;
+`else        
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+    
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+    
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+    
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+    
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule

simple/simplemap_mem_slice_concat/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg [7:0] data_a = 0;
+	reg [7:0] data_b = 0;
+	reg [5:0] addr_a = 0;	
+	reg [5:0] addr_b = 0;
+    reg we_a = 0;
+	reg we_b = 1;	
+    reg re_a = 1;
+	reg re_b = 1;
+	wire [7:0] q_a,q_b;
+	reg mem_init = 0;
+
+    top uut (
+    .data_a(data_a),
+	.data_b(data_b),
+	.addr_a(addr_a),
+	.addr_b(addr_b),
+	.we_a(we_a), 
+	.we_b(we_b), 	
+	.re_a(re_a), 
+	.re_b(re_b), 
+	.clk(clk),
+	.q_a(q_a), 
+	.q_b(q_b)
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    data_a <= data_a + 17;	
+    data_b <= data_b + 5;
+	
+    addr_a <= addr_a + 1;	
+    addr_b <= addr_b + 1;
+    end
+    
+    always @(posedge addr_a) begin
+    #10;
+        if(addr_a > 6'h3E)
+            mem_init <= 1;
+    end
+	
+	always @(posedge clk) begin
+    //#3;
+    we_a <= !we_a; 
+    we_b <= !we_b; 
+    end
+	
+	uut_mem_checker port_a_test(.clk(clk), .init(mem_init), .en(!we_a), .A(q_a));
+    uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .en(!we_b), .A(q_b));
+    
+endmodule
+
+module uut_mem_checker(input clk, input init, input en, input [7:0] A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & init == 1 & A === 8'bXXXXXXXX)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/simplemap_mem_slice_concat/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clk,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+
+	// Port A
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_a)
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+`else
+		if (we_a)
+		begin
+			ram[addr_a] <= 8'bXXXXXXXX;
+			q_a <= 8'bXXXXXXXX;
+		end
+		if (re_b)
+		begin
+			q_a <= ram[addr_a];
+		end
+`endif
+	end
+
+	// Port B
+	always @ (posedge clk)
+	begin
+`ifndef BUG
+		if (we_b)
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+`else
+		if (we_b)
+		begin
+			ram[addr_b] <= 8'bXXXXXXXX;
+			q_b <= 8'bXXXXXXXX;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+`endif
+	end
+
+endmodule

simple/simplemap_reduce/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+       // $dumpfile("testbench.vcd");
+       // $dumpvars(0, testbench);
+
+        #0 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+    reg [1:0] a = 0;
+    reg rst = 0;
+
+
+    top uut (
+		.x(x),
+		.clk(clk),
+		.rst(rst),
+		.a(a)
+    );
+
+
+    always @(posedge clk) begin
+
+    a <= a + 1;
+    end
+
+	always @(posedge clk) begin
+    #2;
+	rst <= !rst;
+    end
+
+	uut_checker q_test(.clk(clk), .en(rst), .A(x));
+endmodule
+
+
+
+module uut_checker(input clk, input en, input A);
+    always @(posedge clk)
+    begin
+        #1;
+        if (en == 1 & A === 1'bz)
+        begin
+            $display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
+            $stop;
+        end
+    end
+endmodule

simple/simplemap_reduce/top.v

+// File: design.v
+// Generated by MyHDL 0.8
+// Date: Tue Dec  3 04:33:14 2013
+
+
+`timescale 1ns/10ps
+
+module top (
+    x,clk,rst,a
+);
+
+output x;
+reg x;
+input clk;
+input [0:0] rst;
+input [0:0] a;
+
+wire rst_or;
+
+assign rst_or = |rst;
+`ifndef BUG
+always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
+    reg i;
+    if (!rst_or) begin
+        i = 0;
+        x = 0;
+    end
+    else begin
+        case (a)
+            2'b00: begin
+				x = 0;
+                i = 0;
+            end
+            2'b01: begin
+                x = i;
+            end
+            2'b10: begin
+                i = 1;
+            end
+            2'b11: begin
+                i = 0;
+            end
+            default: begin
+                x = 0;
+                i = 0;
+            end
+        endcase
+    end
+end
+
+    `else
+always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
+    reg i;
+    if (!rst_or) begin
+        i = 0;
+        x = 0;
+    end
+    else begin
+        case (a)
+            2'b00: begin
+				x = 1'bZ;
+                i = 0;
+            end
+            2'b01: begin
+                x = 1'bZ;
+            end
+            2'b10: begin
+                i = 1;
+            end
+            2'b11: begin
+                i = 0;
+            end
+            default: begin
+                x = 1'bZ;
+                i = 0;
+            end
+        endcase
+    end
+end
+`endif
+endmodule

simple/techmap/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");
+    end
+
+
+    reg [2:0] dinA = 0;
+    wire doutB,doutB1,doutB2,doutB3,doutB4;
+	reg dff,ndff,adff,adffn,dffe = 0;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA[0] ),
+        .pre (dinA[1] ),
+        .clr (dinA[2] ),
+        .b (doutB ),
+        .b1 (doutB1 ),
+        .b2 (doutB2 ),
+        .b3 (doutB3 ),
+        .b4 (doutB4 )
+    );
+
+    always @(posedge clk) begin
+    #3;
+    dinA <= dinA + 1;
+    end
+
+	always @( posedge clk)
+		if ( dinA[2] )
+			dff <= 1'b0;
+		else if ( dinA[1] )
+			dff <= 1'b1;
+		else
+            dff <= dinA[0];
+
+    always @( negedge clk)
+		if ( !dinA[2] )
+			ndff <= 1'b0;
+		else if ( !dinA[1] )
+			ndff <= 1'b1;
+		else
+            ndff <= dinA[0];
+
+    always @( posedge clk, posedge dinA[2] )
+		if ( dinA[2] )
+			adff <= 1'b0;
+		else
+            adff <= dinA[0];
+
+    always @( posedge clk, negedge dinA[2] )
+		if ( !dinA[2] )
+			adffn <= 1'b0;
+		else
+            adffn <= dinA[0];
+
+    always @( posedge clk )
+		if ( dinA[2] )
+            dffe <= dinA[0];
+
+	assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
+    assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
+    assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
+    assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
+    assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
+
+endmodule

simple/techmap/top.v

+(* \\keep_hierarchy *) module adff
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, posedge clr )
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+(* \\techmap_simplemap *)module adffn
+    ( input d, clk, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk, negedge clr )
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else
+            q <= d;
+endmodule
+
+(* \\techmap_maccmap *)module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+`ifndef BUG
+			q <= d;
+`else
+			q <= 1'b0;
+`endif
+endmodule
+
+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk)
+		if ( clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+module ndffnsnr
+    ( input d, clk, pre, clr, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( negedge clk)
+		if ( !clr )
+`ifndef BUG
+			q <= 1'b0;
+`else
+			q <= d;
+`endif
+		else if ( !pre )
+			q <= 1'b1;
+		else
+            q <= d;
+endmodule
+
+
+(* \\top *)module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2,b3,b4
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b )
+    );
+
+ndffnsnr u_ndffnsnr (
+        .clk (clk ),
+        .clr (clr),
+        .pre (pre),
+        .d (a ),
+        .q (b1 )
+    );
+
+adff u_adff (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b2 )
+    );
+
+adffn u_adffn (
+        .clk (clk ),
+        .clr (clr),
+        .d (a ),
+        .q (b3 )
+    );
+
+dffe u_dffe (
+        .clk (clk ),
+        .en (clr),
+        .d (a ),
+        .q (b4 )
+    );
+
+endmodule