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yosys-tests
Commit 596fd6ff by Eddie Hung
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Ooops

parent 6fd5fd38
Showing with 2 additions and 2 deletions
architecture/synth_xilinx_srl/run-test.sh
...@@ -20,8 +20,8 @@ if ! which iverilog > /dev/null ; then ...@@ -20,8 +20,8 @@ if ! which iverilog > /dev/null ; then
fi fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/lfsr/generate.py -O generate_lfsr.py -o /dev/null
#python3 generate_lfsr.py python3 generate_lfsr.py
#python3 ../generate.py python3 ../generate.py
cp ../*.v . cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\ ${MAKE:-make} -f ../../../../tools/autotest.mk $seed !(test21*).v EXTRA_FLAGS="\
-f 'verilog -noblackbox -icells' \ -f 'verilog -noblackbox -icells' \
......
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