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yosys-tests
Commit 4e5320c4 by Miodrag Milanovic
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it was set to be edge, but expected was level

parent b7ccc29f
Showing with 1 additions and 1 deletions
simple/dffc/top.v
module dffcp module dffcp
( input d, clk, pre, clr, output reg q ); ( input d, clk, pre, clr, output reg q );
always @( posedge clk, posedge pre, negedge clr ) always @( posedge clk)
if ( pre ) if ( pre )
q <= 1'b1; q <= 1'b1;
else if ( clr ) else if ( clr )
......
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