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yosys-tests
Unverified Commit b7ccc29f by Miodrag Milanović Committed by GitHub
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Merge pull request #29 from SergeyDegtyar/master 

Fix failed tests
parents 4c1b7236 5fee7bf3
Showing with 451 additions and 165 deletions
architecture/synth_ice40_mem/top.v
......@@ -24,7 +24,7 @@ module top
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("init.txt")
.INIT_FILE("../init.txt")
) \ram.0.0.0 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
......
backends/Makefile
......@@ -52,7 +52,7 @@ $(eval $(call template,write_firrtl_paramod,write_firrtl))
#write_ilang
$(eval $(call template,write_ilang,write_ilang write_ilang_selected))
$(eval $(call template,write_ilang_mem,write_ilang write_ilang_selected))
$(eval $(call template,write_ilang_mem,write_ilang_mem))
$(eval $(call template,write_ilang_mux,write_ilang write_ilang_selected))
$(eval $(call template,write_ilang_fsm,write_ilang write_ilang_selected))
$(eval $(call template,write_ilang_tri,write_ilang write_ilang_selected))
......@@ -79,8 +79,8 @@ $(eval $(call template,write_smt2_shiftx,write_smt2 write_smt2_synth write_smt2_
#write_smv
$(eval $(call template,write_smv,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_wide,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_shift,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_wide,write_smv write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_shift,write_smv_shift))
$(eval $(call template,write_smv_fsm,write_smv write_smv_noproc write_smv_verbose write_smv_tpl))
$(eval $(call template,write_smv_reduce,write_smv_noproc))
$(eval $(call template,write_smv_logic,write_smv write_smv_synth write_smv_noproc write_smv_verbose write_smv_tpl))
......
backends/scripts/write_aiger.ys
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_B.ys
read_verilog -sv ../top.v
aigmap
write_aiger -B aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_I.ys
read_verilog -sv ../top.v
aigmap
write_aiger -I aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_O.ys
read_verilog -sv ../top.v
aigmap
write_aiger -O aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_ascii.ys
read_verilog -sv ../top.v
aigmap
write_aiger -ascii aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_map.ys
read_verilog -sv ../top.v
aigmap
write_aiger -map a.map aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_miter.ys
......@@ -2,4 +2,9 @@ read_verilog -sv ../top_clean.v
synth -top top
aigmap
write_aiger -miter aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_symbols.ys
read_verilog -sv ../top.v
aigmap
write_aiger -symbols aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_aiger_vmap.ys
read_verilog -sv ../top.v
aigmap
write_aiger -vmap a.map aiger.aiger
design -reset
read_verilog -sv ../top_clean.v
aigmap
write_aiger aiger.aiger
synth -top top
write_verilog synth.v
backends/scripts/write_ilang.ys
......@@ -4,4 +4,5 @@ proc
dump -o file.il
write_ilang ilang.ilang
dump -n -o file1.il
synth
write_verilog synth.v
backends/scripts/write_ilang_mem.ys 0 → 100644
read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
dump -n -o file1.il
write_verilog synth.v
backends/scripts/write_smt2.ys
read_verilog ../top.v
proc
memory
write_smt2 smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_bv.ys
read_verilog ../top.v
proc
memory
write_smt2 -bv smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_mem.ys
read_verilog ../top.v
proc
memory
write_smt2 -mem smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_mem_memtest.ys
read_verilog ../top.v
memory_collect
proc
memory
write_smt2 -mem smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_memtest.ys
read_verilog ../top.v
memory_collect
proc
memory
write_smt2 smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_nomem.ys
read_verilog ../top.v
proc
memory
write_smt2 -nomem smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_stbv.ys
read_verilog ../top.v
proc
memory
write_smt2 -stbv smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_stbv_memtest.ys
read_verilog ../top.v
memory_collect
proc
memory
write_smt2 -stbv smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_stdt.ys
read_verilog ../top.v
proc
memory
write_smt2 -stdt smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_tpl.ys
read_verilog ../top.v
proc
memory
write_smt2 -tpl ../top.tpl smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_verbose.ys
read_verilog ../top.v
proc
memory
write_smt2 -verbose smt2.smt2
write_verilog synth.v
backends/scripts/write_smt2_wires.ys
read_verilog ../top.v
proc
memory
write_smt2 -wires smt2.smt2
write_verilog synth.v
backends/scripts/write_smv_shift.ys 0 → 100644
read_verilog ../top.v
proc
write_smv smv.smv
design -reset
read_verilog ../top_clean.v
proc
write_smv smv.smv
write_verilog synth.v
frontends/Makefile
......@@ -39,7 +39,7 @@ $(eval $(call template,read_ilang_tri,read_ilang read_ilang_selected))
$(eval $(call template,read_json,read_json))
$(eval $(call template,read_json_fsm,read_json))
$(eval $(call template,read_json_logic,read_json))
$(eval $(call template,read_json_mem,read_json))
$(eval $(call template,read_json_mem,read_json_mem))
$(eval $(call template,read_json_mux,read_json))
$(eval $(call template,read_json_tri,read_json))
......
frontends/read/testbench.v
......@@ -27,7 +27,7 @@ module testbench;
);
assign patt_out = in[1] + in[2];
assign patt_carry_out = in[1] + patt_out;
assign patt_carry_out = in[0] + patt_out;
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
......
frontends/read/top.v
......@@ -11,7 +11,7 @@ module top
`ifndef BUG
assign A = y + cin;
assign cout = y + A;
assign cout = x + A;
`else
assign {cout,A} = cin - y * x;
......
frontends/read_aiger_latch/testbench.v
......@@ -2,8 +2,8 @@ module testbench;
reg en;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
......@@ -38,6 +38,6 @@ module testbench;
assert_dff lat_test(.clk(en), .test(doutB), .pat(lat));
assert_dff lat_test(.clk(en), .test(doutB), .pat(~lat));
endmodule
frontends/scripts/read_ilang.ys
read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang ilang.ilang
design -reset
......
frontends/scripts/read_ilang_selected.ys
read_verilog ../top.v
proc
memory
dump -o file.il
write_ilang -selected ilang.ilang
design -reset
......
frontends/scripts/read_json.ys
read_verilog ../top.v
proc
write_json json.json
design -reset
read_json json.json
......
frontends/scripts/read_json_mem.ys 0 → 100644
read_verilog ../top.v
write_json json.json
design -reset
read_json json.json
design -reset
read_verilog ../top.v
proc
memory
write_verilog synth.v
regression/issue_00699/top.v
module counter(clk, en);
module top(clk, en);
input clk;
input en;
reg [3:0] X;
......
regression/run.sh
......@@ -21,7 +21,6 @@ if [ "$1" = "issue_00089" ] ||\
[ "$1" = "issue_00594" ] ||\
[ "$1" = "issue_00603" ] ||\
[ "$1" = "issue_00635" ] ||\
[ "$1" = "issue_00699" ] ||\
[ "$1" = "issue_00763" ] ||\
[ "$1" = "issue_00814" ]; then
......@@ -62,6 +61,7 @@ elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00675" ] ||\
[ "$1" = "issue_00685" ] ||\
[ "$1" = "issue_00689" ] ||\
[ "$1" = "issue_00699" ] ||\
[ "$1" = "issue_00708" ] ||\
[ "$1" = "issue_00737" ] ||\
[ "$1" = "issue_00774" ] ||\
......@@ -96,6 +96,7 @@ elif [ "$1" = "issue_00502" ] ||\
elif [ "$1" = "issue_00642" ] ||\
[ "$1" = "issue_00644" ] ||\
[ "$1" = "issue_00689" ] ||\
[ "$1" = "issue_00699" ] ||\
[ "$1" = "issue_00708" ] ||\
[ "$1" = "issue_00826" ] ||\
[ "$1" = "issue_00862" ] ||\
......
regression/scripts/issue_00699.ys
tee -o result.log read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
simple/Makefile
......@@ -102,9 +102,6 @@ $(eval $(call template,extract,extract_cell_attr extract_compat extract_constpor
#extract_counter
$(eval $(call template,extract_counter,extract_counter extract_counter_maxwidth extract_counter_pout))
$(eval $(call template,extract_counter_down,extract_counter extract_counter_maxwidth extract_counter_pout))
$(eval $(call template,extract_counter_negative_reset,extract_counter extract_counter_maxwidth extract_counter_pout))
$(eval $(call template,extract_counter_no_reset,extract_counter extract_counter_maxwidth extract_counter_pout))
$(eval $(call template,extract_counter_sync_reset,extract_counter extract_counter_maxwidth extract_counter_pout))
#shregmap
$(eval $(call template,shregmap,shregmap shregmap_clkpol_any shregmap_clkpol_neg shregmap_clkpol_pos shregmap_enpol_any shregmap_enpol_any_or_none shregmap_enpol_neg shregmap_enpol_none shregmap_enpol_pos shregmap_init shregmap_keep_after shregmap_keep_before shregmap_match shregmap_maxlen shregmap_minlen shregmap_params shregmap_tech shregmap_zinit))
......
simple/attrmap/testbench.v
......@@ -29,6 +29,6 @@ module testbench;
dinA <= !dinA;
end
assert_tri b_test(.en(en), .A(dinA), .B(doutB));
assert_tri out_test(.en(en), .A(dinA), .B(doutB));
endmodule
simple/extract_counter/testbench.v
......@@ -39,7 +39,7 @@ module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
......
simple/extract_counter/top.v
......@@ -11,7 +11,11 @@ reset
if (reset) begin
out <= 8'b0 ;
end else
`ifndef BUG
out <= out + 1;
`else
out <= out - 1'bZ;
`endif
endmodule
simple/extract_counter_down/testbench.v
......@@ -39,7 +39,7 @@ module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
......
simple/extract_counter_down/top.v
......@@ -11,7 +11,11 @@ reset
if (reset) begin
out <= 8'b11111111;
end else
`ifndef BUG
out <= out - 1;
`else
out <= out + 1'bZ;
`endif
endmodule
simple/ice40_dsp_mult_acc/top.v
......@@ -37,10 +37,17 @@ module top
else if (clken)
begin
`ifndef BUG
dataa_reg <= dataa;
datab_reg <= datab;
sload_reg <= sload;
adder_out <= old_result + multa;
`else
dataa_reg <= datab;
datab_reg <= dataa;
sload_reg <= sload;
adder_out <= old_result - multa;
`endif
end
end
endmodule
simple/inout_port/top.v
......@@ -10,10 +10,10 @@ module tristate (en, i, io, o);
assign o = io;
`else
assign io[0] = (en)? ~i : 1'bZ;
assign io[1] = (i)? ~en : 1'bZ;
assign io[0] = (!en)? ~i : 1'bZ;
assign io[1] = (!i)? ~en : 1'bZ;
assign o = ~io;
`endif
......
simple/iopadmap/top.v
......@@ -17,10 +17,10 @@ module tristate (en, i, io, o);
assign o = (en)? io : 2'bZZ;
`else
always @(en or i)
io_buf[0] <= (en)? ~i : 1'bZ;
io_buf[0] <= (!en)? ~i : 1'bZ;
always @(en or i)
io_buf[1] <= (i)? ~en : 1'bZ;
io_buf[1] <= (!i)? ~en : 1'bZ;
assign o = (en)? ~io : 2'bZZ;
`endif
......
simple/memory/top.v
......@@ -7,33 +7,38 @@ module top
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
`ifndef BUG
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
if (re_b)
begin
q_a <= ram[addr_a];
end
`else
if (we_a)
begin
ram[addr_a] <= 8'bXXXXXXXX;
q_a <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`endif
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
`ifndef BUG
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......@@ -42,6 +47,17 @@ module top
begin
q_b <= ram[addr_b];
end
`else
if (we_b)
begin
ram[addr_b] <= 8'bXXXXXXXX;
q_b <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`endif
end
endmodule
endmodule
simple/muxcover/top.v
......@@ -3,7 +3,10 @@ input [7:0] S,
input [255:0] D,
output M256
);
`ifndef BUG
assign M256 = D[S];
`else
assign M256 = S[D];
`endif
endmodule
simple/opt_demorgan_reduce/testbench.v
module testbench;
reg [2:0] in;
reg [6:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire x;
wire [2:0] y;
wire [2:0] cin;
wire patt_out = 0;
wire patt_carry_out = 0;
wire patt_out1 = 0;
wire patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire control;
wire control_patt;
initial begin
// $dumpfile("testbench.vcd");
......@@ -21,28 +27,30 @@ module testbench;
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.x(x),
.y(y),
.cin(cin),
.A(out),
.cout(carryout)
.cout(carryout),
.control(control)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
wire A1,cout1;
wire [2:0] n_y;
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
wire [2:0] n_cin;
// initial begin
// A = 0;
// cout = 0;
// end
assign x = in[0];
assign y = in[3:1];
assign cin = in[6:4];
assign control_patt = x & y & cin;
assert_dff out_test(.clk(in[0]), .test(control),.pat(control_patt));
endmodule
simple/opt_demorgan_reduce/top.v
......@@ -5,7 +5,8 @@ module top
input [2:0] cin,
output A,
output cout
output cout,
output control
);
wire A1,cout1;
......@@ -32,8 +33,16 @@ assign cout1 = cin ? |n_y : ^A;
assign A = A1|y~&(~cin)~^A1;
assign cout = cout1&cin~|(~y);
assign control = x & y & cin;
`else
assign {cout,A} = 1'bZ;
assign A1 = n_y + &(cin);
assign cout1 = cin ? |n_y : ^A;
assign A = A1|y~&(~cin)~^A1;
assign cout = cout1&cin~|(~y);
assign control = x | y | cin;
`endif
endmodule
simple/opt_expr/testbench.v
......@@ -17,6 +17,8 @@ module testbench;
reg dinA = 0;
wire doutB;
wire pre,clr;
reg q = 0;
top uut (
.clk (clk ),
......@@ -31,6 +33,17 @@ module testbench;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
assign pre = 1'b0;
assign clr = 1'b0;
always @( negedge clk, posedge pre, negedge clr )
if ( pre )
q <= 1'b1;
else if ( clr )
q <= 1'b0;
else
q <= dinA;
assert_dff ff_test(.clk(~clk), .test(doutB), .pat(q));
endmodule
simple/opt_expr/top.v
......@@ -23,7 +23,7 @@ dffsr u_dffsr (
.clr (clr),
.pre (pre),
`else
.clr (1'b0),
.clr (1'b1),
.pre (1'b0),
`endif
.d (a ),
......
simple/opt_lut_ice40/top.v
......@@ -9,10 +9,16 @@ module top(
output [2:0] o4,
input s
);
assign o1 = (s ? 0 : a + b);
assign o2 = (s ? a : a - b);
assign o3 = (s ? 4'b1111 : d + c);
assign o4 = (s ? d : c - d);
`ifndef BUG
assign o1 = (s ? 0 : a + b);
assign o2 = (s ? a : a - b);
assign o3 = (s ? 4'b1111 : d + c);
assign o4 = (s ? d : c - d);
`else
assign o1 = (s ? 0 : a * b);
assign o2 = (s ? a : a / b);
assign o3 = (s ? 4'b1111 : d - c);
assign o4 = (s ? d : c + d);
`endif
endmodule
simple/opt_merge_reduce/testbench.v
module testbench;
reg [2:0] in;
reg [6:0] in;
reg patt_out = 0;
reg patt_carry_out = 0;
reg patt_out1 = 0;
reg patt_carry_out1 = 0;
wire x;
wire [2:0] y;
wire [2:0] cin;
wire patt_out = 0;
wire patt_carry_out = 0;
wire patt_out1 = 0;
wire patt_carry_out1 = 0;
wire out = 0;
wire carryout = 0;
wire control;
wire control_patt;
initial begin
// $dumpfile("testbench.vcd");
......@@ -21,28 +27,30 @@ module testbench;
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.x(x),
.y(y),
.cin(cin),
.A(out),
.cout(carryout)
.cout(carryout),
.control(control)
);
always @(posedge in[0]) begin
patt_out1 <= ~in[1] + &in[2];
end
always @(negedge in[0]) begin
patt_carry_out1 <= in[2] ? |in[1] : patt_out;
end
wire A1,cout1;
wire [2:0] n_y;
always @(*) begin
if (in[0])
patt_out <= patt_out|in[1]~&in[2];
end
always @(*) begin
if (~in[0])
patt_carry_out <= patt_carry_out1&in[2]~|in[1];
end
assert_Z out_test(.A(out));
wire [2:0] n_cin;
// initial begin
// A = 0;
// cout = 0;
// end
assign x = in[0];
assign y = in[3:1];
assign cin = in[6:4];
assign control_patt = x & y & cin;
assert_dff out_test(.clk(in[0]), .test(control),.pat(control_patt));
endmodule
simple/opt_merge_reduce/top.v
......@@ -5,7 +5,8 @@ module top
input [2:0] cin,
output A,
output cout
output cout,
output control
);
wire A1,cout1;
......@@ -32,8 +33,16 @@ assign cout1 = cin ? |n_y : ^A;
assign A = A1|y~&(~cin)~^A1;
assign cout = cout1&cin~|(~y);
assign control = x & y & cin;
`else
assign {cout,A} = 1'bZ;
assign A1 = n_y + &(cin);
assign cout1 = cin ? |n_y : ^A;
assign A = A1|y~&(~cin)~^A1;
assign cout = cout1&cin~|(~y);
assign control = x | y | cin;
`endif
endmodule
simple/opt_merge_share_all/testbench.v
......@@ -14,7 +14,7 @@ module testbench;
$display("OKAY");
end
wire clk_o;
reg [4:0] a;
wire [31:0] c;
......@@ -22,13 +22,13 @@ module testbench;
begin
a = a + 3;
end
top uut (clk, a, c);
top uut (clk, a, c,clk_o);
uut_checker c_test(.clk(clk), .A(c), .B(c));
uut_checker c_test(.clk(clk), .A(clk), .B(clk_o));
endmodule
module uut_checker(input clk, input [31:0] A, input [31:0] B);
module uut_checker(input clk, input A, input B);
always @(posedge clk)
begin
#1;
......
simple/opt_merge_share_all/top.v
......@@ -4,7 +4,7 @@
`define assume(_expr_)
`endif
module top(input clk, input [4:0] addr, output reg [31:0] data);
module top(input clk, input [4:0] addr, output reg [31:0] data, output clk_o);
reg [31:0] mem [0:31];
always @(posedge clk)
data <= mem[addr];
......@@ -21,4 +21,9 @@ module top(input clk, input [4:0] addr, output reg [31:0] data);
//`assume((used_dbits & data) == 0);
end
end
`ifndef BUG
assign clk_o = clk;
`else
assign clk_o = ~clk;
`endif
endmodule
simple/proc_arst/top.v
......@@ -15,6 +15,7 @@ input clk;
input rst;
input [1:0] a;
`ifndef BUG
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
......@@ -43,5 +44,34 @@ always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
endcase
end
end
`else
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 1'bZ;
i = 0;
end
2'b01: begin
x = 1'bZ;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 1'bZ;
i = 0;
end
endcase
end
end
`endif
endmodule
simple/proc_arst_reduce/top.v
......@@ -18,7 +18,7 @@ input [1:0] a;
wire rst_or;
assign rst_or = |rst;
`ifndef BUG
always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
......@@ -48,4 +48,34 @@ always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
end
end
`else
always @(posedge clk, negedge rst_or) begin: DESIGN_PROCESSOR
reg i;
if (!rst_or) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 1'bZ;
i = 0;
end
2'b01: begin
x = 1'bZ;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 1'bZ;
i = 0;
end
endcase
end
end
`endif
endmodule
simple/share/top.v
......@@ -7,33 +7,38 @@ module top
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
`ifndef BUG
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
if (re_b)
begin
q_a <= ram[addr_a];
end
`else
if (we_a)
begin
ram[addr_a] <= 8'bXXXXXXXX;
q_a <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`endif
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
`ifndef BUG
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......@@ -42,6 +47,17 @@ module top
begin
q_b <= ram[addr_b];
end
`else
if (we_b)
begin
ram[addr_b] <= 8'bXXXXXXXX;
q_b <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`endif
end
endmodule
endmodule
simple/share_shr/testbench.v
......@@ -15,7 +15,7 @@ module testbench;
end
reg in;
reg in = 0;
wire [7:0] f;
......@@ -39,7 +39,7 @@ module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
......
simple/share_shr/top.v
......@@ -12,8 +12,12 @@ in
always @(posedge clk)
begin
`ifndef BUG
out <= out >> 1;
out[7] <= in;
`else
out <= 8'bZZZZZZZZ;
`endif
end
always @(posedge clk)
......
simple/shregmap/testbench.v
......@@ -15,7 +15,7 @@ module testbench;
end
reg in;
reg in = 0;
wire [7:0] f;
......@@ -39,7 +39,7 @@ module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
......
simple/shregmap/top.v
......@@ -9,8 +9,12 @@ in
always @(posedge clk)
begin
`ifndef BUG
out <= out << 1;
out[0] <= in;
`else
out <= 8'bZZZZZZZZ;
`endif
end
endmodule
simple/shregmap_resetable/testbench.v
......@@ -47,7 +47,7 @@ module assert_expr(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A == 1'bZ)
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
......
simple/shregmap_resetable/top.v
......@@ -19,7 +19,11 @@ module top
end
assign r_next = {s_in, r_reg[N-1:1]};
`ifndef BUG
assign s_out = r_reg[0];
`else
assign s_out = 1'bZ;
`endif
endmodule
simple/submod_mem/top.v
......@@ -7,33 +7,38 @@ module top
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
`ifndef BUG
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
if (re_b)
begin
q_a <= ram[addr_a];
end
`else
if (we_a)
begin
ram[addr_a] <= 8'bXXXXXXXX;
q_a <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`endif
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
`ifndef BUG
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......@@ -42,6 +47,17 @@ module top
begin
q_b <= ram[addr_b];
end
`else
if (we_b)
begin
ram[addr_b] <= 8'bXXXXXXXX;
q_b <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`endif
end
endmodule
endmodule
simple/wreduce_memx/top.v
......@@ -7,33 +7,38 @@ module top
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
`ifndef BUG
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
if (re_b)
if (re_b)
begin
q_a <= ram[addr_a];
end
`else
if (we_a)
begin
ram[addr_a] <= 8'bXXXXXXXX;
q_a <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_a <= ram[addr_a];
end
`endif
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
`ifndef BUG
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......@@ -42,6 +47,17 @@ module top
begin
q_b <= ram[addr_b];
end
`else
if (we_b)
begin
ram[addr_b] <= 8'bXXXXXXXX;
q_b <= 8'bXXXXXXXX;
end
if (re_b)
begin
q_b <= ram[addr_b];
end
`endif
end
endmodule
endmodule
simple/zinit/testbench.v
......@@ -11,13 +11,17 @@ module testbench;
#5 clk = 0;
end
$display("OKAY");
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
reg dff = 0;
reg ndff= 1;
reg adff= 0;
reg adffn = 1'bX;
reg dffe = 1'bZ;
top uut (
.clk (clk ),
......
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