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lvzhengyang
yosys-tests
Commits
4d0182cb
Commit
4d0182cb
authored
Sep 16, 2019
by
SergeyDegtyar
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Fix failed tests
parent
897d1f1d
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3 changed files
with
17 additions
and
11 deletions
+17
-11
architecture/ice40_wrapcarry/testbench.v
+8
-10
architecture/ice40_wrapcarry/top.v
+0
-1
frontends/scripts/read_aiger_map.ys
+9
-0
No files found.
architecture/ice40_wrapcarry/testbench.v
View file @
4d0182cb
...
@@ -24,24 +24,22 @@ module testbench;
...
@@ -24,24 +24,22 @@ module testbench;
)
;
)
;
//assign poutA = in[3:0] % in[7:4];
assign
poutB
=
in
[
3
:
0
]
/
in
[
7
:
4
]
;
assign
poutB
=
in
[
3
:
0
]
/
in
[
7
:
4
]
;
//check_comb mod_test(outA, poutA);
check_comb
div_test
(
in
[
7
:
4
]
,
outB
,
poutB
)
;
check_comb
div_test
(
outB
,
poutB
)
;
assert_comb
div2_test
(
outB
[
2
]
,
poutB
[
2
])
;
endmodule
endmodule
module
check_comb
(
input
[
3
:
0
]
test
,
input
[
3
:
0
]
pat
)
;
module
check_comb
(
input
[
3
:
0
]
div
,
input
[
3
:
0
]
test
,
input
[
3
:
0
]
pat
)
;
always
@*
always
@*
begin
begin
#
1
;
#
1
;
if
(
test
!==
pat
)
if
(
div
!=
4'b0000
)
begin
if
(
test
!==
pat
)
$
display
(
"ERROR: ASSERTION FAILED in %m:"
,
$
time
,
" "
,
test
,
" "
,
pat
)
;
begin
$
stop
;
$
display
(
"ERROR: ASSERTION FAILED in %m:"
,
$
time
,
" "
,
test
,
" "
,
pat
)
;
end
$
stop
;
end
end
end
endmodule
endmodule
architecture/ice40_wrapcarry/top.v
View file @
4d0182cb
...
@@ -7,7 +7,6 @@ module top
...
@@ -7,7 +7,6 @@ module top
output
[
3
:
0
]
B
output
[
3
:
0
]
B
)
;
)
;
//assign A = x % y;
assign
B
=
x
/
y
;
assign
B
=
x
/
y
;
endmodule
endmodule
frontends/scripts/read_aiger_map.ys
0 → 100644
View file @
4d0182cb
read_verilog -sv ../top.v
aigmap
write_aiger aiger.aiger
design -reset
read_aiger -map aig.map aiger.aiger
design -reset
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
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