Fix failed tests

architecture/ice40_wrapcarry/testbench.v

@@ -24,24 +24,22 @@ module testbench;
 	);
 
 
-	//assign poutA =  in[3:0] % in[7:4];
 	assign poutB =  in[3:0] / in[7:4];
 
-	//check_comb mod_test(outA, poutA);
-	check_comb div_test(outB, poutB);
-	assert_comb div2_test(outB[2], poutB[2]);
+	check_comb div_test(in[7:4], outB, poutB);
 
 endmodule
 
-module check_comb(input [3:0] test, input [3:0] pat);
+module check_comb(input [3:0] div, input [3:0] test, input [3:0] pat);
     always @*
     begin
         #1;
-        if (test !== pat)
-        begin
-            $display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
-            $stop;
-        end
+        if (div != 4'b0000)
+			if (test !== pat)
+			begin
+				$display("ERROR: ASSERTION FAILED in %m:",$time," ",test," ",pat);
+				$stop;
+			end
     end
 endmodule
 

architecture/ice40_wrapcarry/top.v

@@ -7,7 +7,6 @@ module top
  output [3:0] B
  );
 
-//assign A =  x % y;
 assign B =  x / y;
 
 endmodule

frontends/scripts/read_aiger_map.ys

+read_verilog -sv ../top.v
+aigmap
+write_aiger aiger.aiger
+design -reset
+read_aiger -map aig.map aiger.aiger
+design -reset
+read_verilog -sv ../top.v
+synth -top top
+write_verilog synth.v