Commit 6812a322 by SergeyDegtyar

Add tests for 'synth -abc9'

parent e00da20f
......@@ -224,8 +224,8 @@ $(eval $(call template, prep, prep prep_top prep_auto_top prep_flatten prep_ifx
$(eval $(call template_error, prep_error, prep_error))
#synth
$(eval $(call template, synth, synth synth_top synth_auto_top synth_encfile synth_run synth_run_full synth_flatten synth_lut synth_nofsm synth_noabc synth_noabc_lut synth_noalumacc synth_nordff synth_noshare))
$(eval $(call template_error, synth_error, synth_error))
$(eval $(call template, synth, synth synth_top synth_auto_top synth_encfile synth_run synth_run_full synth_flatten synth_lut synth_nofsm synth_noabc synth_noabc_lut synth_noalumacc synth_nordff synth_noshare synth_abc9))
$(eval $(call template_error, synth_error, synth_error synth_abc9_no_lut))
#simplemap
$(eval $(call template, simplemap, simplemap simplemap_top simplemap_slice_concat))
......
......@@ -68,6 +68,8 @@ if echo "$1" | grep ".*_error"; then
expected_string="ERROR: More than one module selected:"
elif [ "$2" = "synth_error" ]; then
expected_string="ERROR: This command only operates on fully selected designs!"
elif [ "$2" = "synth_abc9_no_lut" ]; then
expected_string="ERROR: ABC9 flow only supported for FPGA synthesis (using '-lut' option)"
elif [ "$2" = "zinit_failed_to_handle" ]; then
expected_string="ERROR: Failed to handle init bit"
fi
......
read_verilog ../top.v
synth -abc9 -lut 5
write_verilog synth.v
read_verilog ../top.v
synth -abc9
write_verilog synth.v
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