Skip to content

Y
yosys-tests
Unverified Commit 3842e7dc by Miodrag Milanović Committed by GitHub
Options

Merge pull request #83 from SergeyDegtyar/review_simple_group 

Review simple group
parents 92f409b3 7703889b
Showing with 330 additions and 1428 deletions
simple/.gitignore
*/work_*/
/.stamp
/run-test.mk
simple/scripts/aigmap.ys → simple/aigmap/aigmap.ys
read_verilog ../top.v
tee -o result1.out dump
aigmap
tee -o result.log dump
tee -o result.out dump
proc
aigmap
synth -top top
aigmap
write_verilog synth.v
simple/scripts/aigmap_nand.ys → simple/aigmap/aigmap_nand.ys
read_verilog ../top.v
tee -o result1.out dump
aigmap -nand
tee -o result.log dump
tee -o result.out dump
proc
aigmap -nand
synth -top top
aigmap -nand
write_verilog synth.v
simple/aigmap/aigmap_select.ys 0 → 100644
read_verilog ../top.v
tee -o result1.out dump
aigmap -select
tee -o result.out dump
proc
aigmap -select
synth -top top
simple/aigmap/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] D = 1;
reg [3:0] S = 0;
wire M2,M4,M8,M16;
top uut (
.S (S ),
.D (D ),
.M2 (M2 ),
.M4 (M4 ),
.M8 (M8 ),
.M16 (M16 )
);
always @(posedge clk) begin
//#3;
D <= {D[14:0],D[15]};
//D <= D <<< 1;
S <= S + 1;
end
assert_tri m2_test(.en(clk), .A(D[0]|D[1]), .B(M2));
assert_tri m4_test(.en(clk), .A(D[0]|D[1]|D[2]|D[3]), .B(M4));
assert_tri m8_test(.en(clk), .A(!S[3]), .B(M8));
assert_tri m16_test(.en(clk), .A(1'b1), .B(M16));
endmodule
simple/aigmap/top.v
......@@ -2,15 +2,9 @@ module mux2 (S,A,B,Y);
input S;
input A,B;
output reg Y;
`ifndef BUG
always @(*)
Y = (S)? B : A;
`else
always @(*)
Y = (~S)? B : A;
`endif
endmodule
module mux4 ( S, D, Y );
......@@ -28,11 +22,7 @@ begin
case( S )
0 : Y = D[0];
1 : Y = D[1];
`ifndef BUG
2 : Y = D[2];
`else
2 : Y = D[3];
`endif
3 : Y = D[3];
endcase
end
......@@ -56,11 +46,7 @@ begin
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
......@@ -69,7 +55,7 @@ end
endmodule
module mux16 (D, S, Y);
module mux16 (D, S, Y);
input [15:0] D;
input [3:0] S;
output Y;
......@@ -77,7 +63,7 @@ module mux16 (D, S, Y);
reg Y;
wire[3:0] S;
wire[15:0] D;
always @*
begin
case( S )
......@@ -85,11 +71,7 @@ always @*
1 : Y = D[1];
2 : Y = D[2];
3 : Y = D[3];
`ifndef BUG
4 : Y = D[4];
`else
4 : Y = D[7];
`endif
5 : Y = D[5];
6 : Y = D[6];
7 : Y = D[7];
......@@ -103,7 +85,7 @@ always @*
15 : Y = D[15];
endcase
end
endmodule
......@@ -119,20 +101,20 @@ mux2 u_mux2 (
.B (D[1]),
.Y (M2)
);
mux4 u_mux4 (
.S (S[1:0]),
.D (D[3:0]),
.Y (M4)
);
mux8 u_mux8 (
.S (S[2:0]),
.D (D[7:0]),
.Y (M8)
);
mux16 u_mux16 (
.S (S[3:0]),
.D (D[15:0]),
......
simple/alu/gates.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -g gates
select -assert-count 98 t:$_ANDNOT_
select -assert-count 465 t:$_AND_
select -assert-count 32 t:$_DFF_P_
select -assert-count 786 t:$_NAND_
select -assert-count 43 t:$_NOR_
select -assert-count 3 t:$_NOT_
select -assert-count 92 t:$_ORNOT_
select -assert-count 257 t:$_OR_
select -assert-count 18 t:$_XNOR_
select -assert-count 26 t:$_XOR_
simple/alu/luts.ys 0 → 100644
read_verilog ../top.v
synth -top top
abc -lut 4
select -assert-count 32 t:$_DFF_P_
select -assert-count 689 t:$lut
simple/alu/testbench.v deleted 100644 → 0
module testbench;
reg clock;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clock = 0;
repeat (10000) begin
#5 clock = 1;
#5 clock = 0;
end
$display("OKAY");
end
reg [31:0] dinA;
reg [31:0] dinB;
reg [2:0] opcode;
wire [31:0] dout;
top uut (
.clock (clock ),
.dinA (dinA ),
.dinB (dinB ),
.opcode (opcode),
.dout (dout )
);
reg [31:0] ref;
always @(posedge clock) begin
case (opcode)
0: ref <= dinA + dinB;
1: ref <= dinA - dinB;
2: ref <= dinA >> dinB;
3: ref <= $signed(dinA) >>> dinB;
4: ref <= dinA << dinB;
5: ref <= dinA & dinB;
6: ref <= dinA | dinB;
7: ref <= dinA ^ dinB;
endcase
end
reg [127:0] rngstate = 1;
reg [63:0] rng;
task rngnext;
// xorshift128plus
reg [63:0] x, y;
begin
{y, x} = rngstate;
rngstate[63:0] = y;
x ^= x << 23;
rngstate[63:0] = x ^ y ^ (x >> 17) ^ (y >> 26);
rng = rngstate[63:0] + y;
end
endtask
initial begin
dinA <= 1;
dinB <= 2;
opcode <= 0;
repeat (100)
rngnext;
forever @(posedge clock) begin
if (ref != dout) begin
$display("ERROR at %t: A=%b B=%b OP=%b OUT=%b (expected %b)",
$time, dinA, dinB, opcode, dout, ref);
$stop;
end
dinA <= rng;
rngnext;
dinB <= rng;
rngnext;
opcode <= rng;
rngnext;
end
end
endmodule
simple/alu/top.v
......@@ -13,11 +13,7 @@ module top (
4: dout <= dinA << dinB;
5: dout <= dinA & dinB;
6: dout <= dinA | dinB;
`ifndef BUG
7: dout <= dinA ^ dinB;
`else
7: dout <= -dinA ^ dinB;
`endif
endcase
end
endmodule
simple/async2sync/async2sync.ys 0 → 100644
read_verilog ../top.v
proc
select -assert-count 2 t:$dffsr
async2sync
select -assert-none t:$dffsr
simple/async2sync/async2sync_latch.ys 0 → 100644
read_verilog ../top_latch.v
proc
select -assert-count 4 t:$dlatch
async2sync
select -assert-none t:$dlatch
simple/async2sync/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/async2sync/top.v
......@@ -5,11 +5,7 @@ module adff
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -21,11 +17,7 @@ module adffn
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -37,11 +29,7 @@ module dffe
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
......@@ -51,11 +39,7 @@ module dffsr
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
......@@ -69,11 +53,7 @@ module ndffnsnr
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
......@@ -95,7 +75,7 @@ dffsr u_dffsr (
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
......@@ -103,21 +83,21 @@ ndffnsnr u_ndffnsnr (
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
......
simple/clk2fflogic_latch/top.v → simple/async2sync/top_latch.v
......@@ -5,11 +5,7 @@ module alat
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (en)
q <= d;
endmodule
......@@ -21,11 +17,7 @@ module alatn
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (!en)
q <= d;
endmodule
......@@ -37,11 +29,7 @@ module latsr
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else if ( en )
......@@ -55,11 +43,7 @@ module nlatsr
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else if ( !en )
......@@ -81,7 +65,7 @@ latsr u_latsr (
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
......@@ -89,19 +73,19 @@ nlatsr u_nlatsr (
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
simple/scripts/attrmap.ys → simple/attrmap/attrmap.ys
read_verilog ../top.v
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
proc
tee -o result1.out dump
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
write_verilog synth.v
tee -o result.out dump
simple/attrmap/attrmap_del.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result1.out dump
attrmap -tocase keep -remove keep="true"
tee -o result.out dump
simple/attrmap/attrmap_del_n.pat 0 → 100644
attribute \\keep "true"
simple/scripts/attrmap_modattr.ys → simple/attrmap/attrmap_modattr.ys
read_verilog ../top.v
proc
attrmap -modattr -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0 -rename keep keep_attr
write_verilog synth.v
tee -o result.out dump
simple/attrmap/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.en (en ),
.a (dinA ),
.b (doutB )
);
always @(posedge en) begin
//#3;
dinA <= !dinA;
end
assert_tri out_test(.en(en), .A(dinA), .B(doutB));
endmodule
simple/attrmap/top.v
......@@ -4,13 +4,7 @@ module top (en, a, b);
output reg b;
(* keep = "true" *) wire int_dat;
`ifndef BUG
always @(en or a)
b <= (en)? a : 1'bZ;
`else
always @(en or a)
b <= (en)? ~a : 1'bZ;
`endif
endmodule
simple/clk2fflogic/clk2fflogic.ys 0 → 100644
read_verilog ../top.v
proc
select -assert-any t:$dffsr
select -assert-any t:$dff
select -assert-any t:$adff
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dffsr
select -assert-none t:$dff
select -assert-none t:$adff
select -assert-any t:$ff
simple/clk2fflogic/clk2fflogic_latch.ys 0 → 100644
read_verilog ../top_latch.v
proc
select -assert-any t:$dlatch
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dlatch
select -assert-any t:$ff
simple/clk2fflogic/clk2fflogic_mem.ys 0 → 100644
read_verilog ../top_mem.v
memory_collect
proc
select -assert-any t:$dff
select -assert-none t:$ff
clk2fflogic
select -assert-none t:$dff
select -assert-any t:$ff
simple/clk2fflogic/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/clk2fflogic/top.v
......@@ -5,11 +5,7 @@ module adff
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -21,11 +17,7 @@ module adffn
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -37,11 +29,7 @@ module dffe
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
......@@ -51,11 +39,7 @@ module dffsr
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
......@@ -69,11 +53,7 @@ module ndffnsnr
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
......@@ -95,7 +75,7 @@ dffsr u_dffsr (
.d (a ),
.q (b )
);
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
......@@ -103,21 +83,21 @@ ndffnsnr u_ndffnsnr (
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
......
simple/flowmap_latch/top.v → simple/clk2fflogic/top_latch.v
......@@ -5,11 +5,7 @@ module alat
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (en)
q <= d;
endmodule
......@@ -21,11 +17,7 @@ module alatn
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if (!en)
q <= d;
endmodule
......@@ -37,11 +29,7 @@ module latsr
end
always @(*)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else if ( en )
......@@ -55,11 +43,7 @@ module nlatsr
end
always @(*)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else if ( !en )
......@@ -81,7 +65,7 @@ latsr u_latsr (
.d (a ),
.q (b )
);
nlatsr u_nlatsr (
.en (en ),
.clr (clr),
......@@ -89,19 +73,19 @@ nlatsr u_nlatsr (
.d (a ),
.q (b1 )
);
alat u_alat (
.en (en ),
.clr (clr),
.d (a ),
.q (b2 )
);
alatn u_alatn (
.en (en ),
.clr (clr),
.d (a ),
.q (b3 )
);
endmodule
simple/clk2fflogic_mem/top.v → simple/clk2fflogic/top_mem.v
......@@ -7,33 +7,25 @@ module top
);
// Declare the RAM variable
reg [7:0] ram[63:0];
// Port A
always @ (posedge clk)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
if (we_a)
begin
ram[addr_a] <= data_a;
q_a <= data_a;
end
else
else
begin
q_a <= ram[addr_a];
end
end
// Port B
always @ (posedge clk)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
if (we_b)
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......@@ -43,5 +35,5 @@ module top
q_b <= ram[addr_b];
end
end
endmodule
endmodule
simple/clk2fflogic_latch/testbench.v deleted 100644 → 0
module testbench;
reg en;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 en = 0;
repeat (10000) begin
#5 en = 1;
#5 en = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3;
reg lat,nlat,alat,alatn = 0;
top uut (
.en (en ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 )
);
always @(posedge en) begin
#3;
dinA <= dinA + 1;
end
always @( en or dinA[0] or dinA[1] or dinA[2] )
if ( dinA[2] )
lat <= 1'b0;
else if ( dinA[1] )
lat <= 1'b1;
else if ( en )
lat <= dinA[0];
always @( en or dinA[0] or dinA[1] or dinA[2] )
if ( !dinA[2] )
nlat <= 1'b0;
else if ( !dinA[1] )
nlat <= 1'b1;
else if (!en)
nlat <= dinA[0];
always @( en or dinA[0] or dinA[2] )
if ( dinA[2] )
alat <= 1'b0;
else if (en)
alat <= dinA[0];
always @( en or dinA[0] or dinA[2] )
if ( !dinA[2] )
alatn <= 1'b0;
else if (!en)
alatn <= dinA[0];
assert_dff lat_test(.clk(en), .test(doutB), .pat(lat));
assert_dff nlat_test(.clk(en), .test(doutB1), .pat(nlat));
assert_dff alat_test(.clk(en), .test(doutB2), .pat(alat));
assert_dff alatn_test(.clk(en), .test(doutB3), .pat(alatn));
endmodule
simple/clk2fflogic_mem/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] data_a = 0;
reg [7:0] data_b = 0;
reg [5:0] addr_a = 0;
reg [5:0] addr_b = 0;
reg we_a = 0;
reg we_b = 1;
wire [7:0] q_a,q_b;
top uut (
.data_a(data_a),
.data_b(data_b),
.addr_a(addr_a),
.addr_b(addr_b),
.we_a(we_a),
.we_b(we_b),
.clk(clk),
.q_a(q_a),
.q_b(q_b)
);
always @(posedge clk) begin
#3;
data_a <= data_a + 17;
data_b <= data_b + 5;
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
end
always @(posedge clk) begin
//#3;
we_a <= !we_a;
we_b <= !we_b;
end
uut_mem_checker port_a_test(.clk(clk), .en(!we_a), .A(q_a));
uut_mem_checker port_b_test(.clk(clk), .en(!we_b), .A(q_b));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
simple/common.v deleted 100644 → 0
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#1;
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_X(input clk, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
simple/scripts/design_import.ys → simple/design_import/design_import.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
design -save top
design -import top
write_verilog synth.v
simple/scripts/design_import_as.ys → simple/design_import/design_import_as.ys
......@@ -2,4 +2,4 @@ read_verilog ../top.v
proc
design -save top
design -import top -as top_new
write_verilog synth.v
simple/design_import/testbench.v deleted 100644 → 0
module testbench;
reg [7:0] in;
wire pi_and,i_and;
wire pi_or,i_or;
wire pi_xor,i_xor;
wire pi_nand,i_nand;
wire pi_nor,i_nor;
wire pi_xnor,i_xnor;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in),
.o_and(i_and),
.o_or(i_or),
.o_xor(i_xor),
.o_nand(i_nand),
.o_nor(i_nor),
.o_xnor(i_xnor)
);
assign pi_and = &in;
assign pi_or = |in;
assign pi_xor = ^in;
assign pi_nand = ~&in;
assign pi_nor = ~|in;
assign pi_xnor = ~^in;
assert_comb and_test(.A(pi_and), .B(i_and));
endmodule
simple/design_import/top.v
......@@ -10,20 +10,11 @@ module top
output o_xnor
);
`ifndef BUG
assign o_and = &x;
assign o_or = |x;
assign o_xor = ^x;
assign o_nand = ~&x;
assign o_nor = ~|x;
assign o_xnor = ~^x;
`else
assign o_and = ~&x;
assign o_or = &x;
assign o_xor = ~^x;
assign o_nand = &x;
assign o_nor = ^x;
assign o_xnor = ~&x;
`endif
endmodule
simple/dff2dffe/dff2dffe_error_fail.pat 0 → 100644
ERROR: No cell types matched pattern '$ff'.
simple/scripts/dff2dffe_unmap.ys → simple/dff2dffe/dff2dffe_unmap.ys
......@@ -2,11 +2,14 @@ read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap
tee -o result.log dump
select -assert-none t:$dffe
dump
synth -top top
dff2dffe
dff2dffe -unmap
select -assert-none t:$dffe
flatten
opt
opt_rmdff
write_verilog synth.v
simple/scripts/dff2dffe_unmap_direct.ys → simple/dff2dffe/dff2dffe_unmap_direct.ys
......@@ -3,11 +3,12 @@ proc
dff2dffe
dff2dffe -direct $dff $dffe
dff2dffe -unmap
tee -o result.log dump
dump
synth -top top
dff2dffe -direct $_DFF_P_ $_DFFE_PP_
dff2dffe -unmap
select -assert-none t:$_DFFE_PP_
flatten
opt
opt_rmdff
write_verilog synth.v
simple/scripts/dff2dffs.ys → simple/dff2dffe/dff2dffe_unmap_direct_match.ys
read_verilog ../top.v
proc
techmap
dff2dffs
design -reset
read_verilog ../top.v
synth -top top
dff2dffe -direct-match $_DFF_P_
dff2dffe -unmap
select -assert-none t:$dffe
flatten
opt
opt_rmdff
write_verilog synth.v
simple/scripts/dff2dffe_unmap_mince.ys → simple/dff2dffe/dff2dffe_unmap_mince.ys
......@@ -2,11 +2,15 @@ read_verilog ../top.v
proc
dff2dffe
dff2dffe -unmap-mince 2
tee -o result.log dump
select -assert-none t:$dffe
dump
synth -top top
dff2dffe
dff2dffe -unmap-mince 2
select -assert-none t:$dffe
flatten
opt
opt_rmdff
write_verilog synth.v
simple/dff2dffe_error/top.v → simple/dff2dffe/top.v
......@@ -5,11 +5,7 @@ module adff
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -21,11 +17,7 @@ module adffn
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -37,11 +29,7 @@ module dffe
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
......@@ -51,11 +39,7 @@ module dffsr
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
......@@ -69,11 +53,7 @@ module ndffnsnr
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
......
simple/dff2dffe_error/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/dff2dffe_unmap/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk, posedge dinA[1], posedge dinA[2] )
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk, negedge dinA[1], negedge dinA[2] )
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/dff2dffs/dff2dffs.ys 0 → 100644
read_verilog ../top.v
proc
techmap
tee -o result1.out stat
dff2dffs
select -assert-none t:$_DFF_N_
tee -o result.out stat
simple/dff2dffs/dff2dffs_match_init.ys 0 → 100644
read_verilog ../top.v
proc
techmap
tee -o result1.out stat
dff2dffs -match-init
tee -o result.out stat
simple/dff2dffs/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk)
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk)
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/dff2dffs/top.v
......@@ -5,11 +5,7 @@ module adff
end
always @( posedge clk, posedge clr )
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -21,11 +17,7 @@ module adffn
end
always @( posedge clk, negedge clr )
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else
q <= d;
endmodule
......@@ -37,11 +29,7 @@ module dffe
end
always @( posedge clk )
if ( en )
`ifndef BUG
q <= d;
`else
q <= 1'b0;
`endif
endmodule
module dffsr
......@@ -51,17 +39,37 @@ module dffsr
end
always @( posedge clk)
if ( clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffs
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffns
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
......@@ -69,11 +77,35 @@ module ndffnsnr
end
always @( negedge clk)
if ( !clr )
`ifndef BUG
q <= 1'b0;
`else
q <= d;
`endif
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
......
simple/dff_d0/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.b (doutB )
);
always @(posedge clk) begin
#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b0));
endmodule
simple/dffc/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
function [31:0] xorshift32;
input [31:0] arg;
begin
xorshift32 = arg;
// Xorshift32 RNG, doi:10.18637/jss.v008.i14
xorshift32 = xorshift32 ^ (xorshift32 << 13);
xorshift32 = xorshift32 ^ (xorshift32 >> 17);
xorshift32 = xorshift32 ^ (xorshift32 << 5);
end
endfunction
reg [31:0] rng = 123456789;
always @(posedge clk) rng <= xorshift32(rng);
wire dinA = xorshift32(rng * 5);
wire dinC = xorshift32(rng * 7);
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.c (dinC),
.b (doutB )
);
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
endmodule
simple/dffcp/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.b (doutB )
);
always @(posedge clk) begin
#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
endmodule
simple/dffr/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.b (doutB )
);
always @(posedge clk) begin
#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b0));
endmodule
simple/dffsr/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.b (doutB )
);
always @(posedge clk) begin
#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
endmodule
simple/scripts/dffsr2dff.ys → simple/dffsr2dff/dffsr2dff.ys
......@@ -11,4 +11,4 @@ flatten
opt
opt_rmdff
dffsr2dff
write_verilog synth.v
simple/dffsr2dff/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.b (doutB )
);
always @(posedge clk) begin
#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
endmodule
simple/dffsr2dff/top.v
......@@ -17,13 +17,8 @@ output b
dffsr u_dffsr (
.clk (clk ),
`ifndef BUG
.clr (1'b1),
.pre (1'b1),
`else
.clr (1'b0),
.pre (1'b0),
`endif
.d (a ),
.q (b )
);
......
simple/scripts/expose_cut.ys → simple/expose/expose_cut.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -cut
write_verilog synth.v
simple/scripts/expose_dff.ys → simple/expose/expose_dff.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -dff
write_verilog synth.v
simple/expose/expose_dff_dff.ys 0 → 100644
read_verilog ../top_dff.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
simple/expose/expose_dff_dffr.ys 0 → 100644
read_verilog ../top_dffr.v
synth -top top
proc
flatten
opt
opt_rmdff
expose -dff
simple/scripts/expose_evert.ys → simple/expose/expose_evert.ys
......@@ -8,4 +8,4 @@ flatten
opt
opt_rmdff
expose -evert
write_verilog synth.v
simple/scripts/expose_evert_dff.ys → simple/expose/expose_evert_dff.ys
......@@ -8,4 +8,4 @@ flatten
opt
opt_rmdff
expose -evert-dff
write_verilog synth.v
simple/scripts/expose_evert_dff_shared.ys → simple/expose/expose_evert_dff_shared.ys
......@@ -7,7 +7,3 @@ flatten
opt
opt_rmdff
expose -evert-dff
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple/scripts/expose_evert_shared.ys → simple/expose/expose_evert_shared.ys
......@@ -6,4 +6,4 @@ opt
opt_rmdff
expose -evert -shared
expose -shared -evert
write_verilog synth.v
simple/scripts/dff.ys → simple/expose/expose_input.ys
read_verilog ../top.v
synth -top top
expose -input
proc
flatten
opt
opt_rmdff
write_verilog synth.v
expose -input
simple/scripts/expose_sep.ys → simple/expose/expose_sep.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -sep |
write_verilog synth.v
simple/scripts/expose_shared.ys → simple/expose/expose_shared.ys
......@@ -5,4 +5,4 @@ flatten
opt
opt_rmdff
expose -shared
write_verilog synth.v
simple/expose/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.b (doutB )
);
always @(posedge clk) begin
#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b0));
endmodule
simple/expose/top.v
module dffr
( input d, clk, rst, output reg q );
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
module adffn
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
if ( rst )
if ( en )
q <= d;
endmodule
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk)
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input a,
output b
output b,b1,b2,b3,b4
);
dffr u_dffr (
.clk (clk),
`ifndef BUG
.rst (1'b1),
`else
.rst (1'b0),
`endif
dffsr u_dffsr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b )
);
endmodule
ndffnsnr u_ndffnsnr (
.clk (clk ),
.clr (clr),
.pre (pre),
.d (a ),
.q (b1 )
);
adff u_adff (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b2 )
);
adffn u_adffn (
.clk (clk ),
.clr (clr),
.d (a ),
.q (b3 )
);
dffe u_dffe (
.clk (clk ),
.en (clr),
.d (a ),
.q (b4 )
);
endmodule
simple/expose_dff/top.v → simple/expose/top_dff.v
module dffr
module dff
( input d, clk, output reg q );
always @( posedge clk )
q <= d;
......@@ -11,13 +11,9 @@ input a,
output b
);
dffr u_dffr (
dff u_dff (
.clk (clk),
`ifndef BUG
.d (a ),
`else
.d (1'b1 ),
`endif
.q (b )
);
......
simple/dffr/top.v → simple/expose/top_dffr.v
......@@ -16,11 +16,7 @@ output b
dffr u_dffr (
.clk (clk),
`ifndef BUG
.rst (1'b1),
`else
.rst (1'b0),
`endif
.d (a ),
.q (b )
);
......
simple/expose_dff/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg dinA = 0;
wire doutB;
top uut (
.clk (clk ),
.a (dinA ),
.b (doutB )
);
always @(posedge clk) begin
//#3;
dinA <= !dinA;
end
assert_dff ff_test(.clk(clk), .test(doutB), .pat(!dinA));
endmodule
simple/expose_ffs/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [2:0] dinA = 0;
wire doutB,doutB1,doutB2,doutB3,doutB4;
reg dff,ndff,adff,adffn,dffe = 0;
top uut (
.clk (clk ),
.a (dinA[0] ),
.pre (dinA[1] ),
.clr (dinA[2] ),
.b (doutB ),
.b1 (doutB1 ),
.b2 (doutB2 ),
.b3 (doutB3 ),
.b4 (doutB4 )
);
always @(posedge clk) begin
#3;
dinA <= dinA + 1;
end
always @( posedge clk)
if ( dinA[2] )
dff <= 1'b0;
else if ( dinA[1] )
dff <= 1'b1;
else
dff <= dinA[0];
always @( negedge clk)
if ( !dinA[2] )
ndff <= 1'b0;
else if ( !dinA[1] )
ndff <= 1'b1;
else
ndff <= dinA[0];
always @( posedge clk, posedge dinA[2] )
if ( dinA[2] )
adff <= 1'b0;
else
adff <= dinA[0];
always @( posedge clk, negedge dinA[2] )
if ( !dinA[2] )
adffn <= 1'b0;
else
adffn <= dinA[0];
always @( posedge clk )
if ( dinA[2] )
dffe <= dinA[0];
assert_dff dff_test(.clk(clk), .test(doutB), .pat(dff));
assert_dff ndff_test(.clk(clk), .test(doutB1), .pat(ndff));
assert_dff adff_test(.clk(clk), .test(doutB2), .pat(adff));
assert_dff adffn_test(.clk(clk), .test(doutB3), .pat(adffn));
assert_dff dffe_test(.clk(clk), .test(doutB4), .pat(dffe));
endmodule
simple/extract/extract_args_to_perm_fail.pat 0 → 100644
ERROR: Arguments to -perm are not a valid permutation!
simple/extract/extract_cant_open_output_fail.pat 0 → 100644
ERROR: Can't open output file `tt/out'.
simple/scripts/extract_cell_attr.ys → simple/extract/extract_cell_attr.ys
read_verilog ../top.v
extract -map ../top.v -cell_attr attr
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple/scripts/extract_compat.ys → simple/extract/extract_compat.ys
read_verilog ../top.v
extract -map ../top.v -compat $dff a
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple/scripts/extract_constports.ys → simple/extract/extract_constports.ys
read_verilog ../top.v
extract -map ../top.v -constports
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple/scripts/extract_ignore_param.ys → simple/extract/extract_ignore_param.ys
read_verilog ../top.v
extract -map ../top.v -ignore_param $dff param
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple/scripts/extract_ignore_parameters.ys → simple/extract/extract_ignore_parameters.ys
read_verilog ../top.v
extract -map ../top.v -ignore_parameters
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple/scripts/extract_map.ys → simple/extract/extract_map.ys
read_verilog ../top.v
extract -map ../top.v
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple/extract/extract_map_and_mine_fail.pat 0 → 100644
ERROR: You cannot mix -map and -mine.
simple/scripts/extract_map_design.ys → simple/extract/extract_map_design.ys
read_verilog ../top.v
design -save top_test
extract -map %top_test
design -reset
read_verilog ../top.v
proc
write_verilog synth.v
simple/scripts/extract_mine.ys → simple/extract/extract_mine.ys
read_verilog ../top.v
extract -mine out.ilang
write_verilog synth.v
simple/extract/extract_mine_and_map_fail.pat 0 → 100644
ERROR: You cannot mix -map and -mine.
simple/scripts/extract_mine_cells_span.ys → simple/extract/extract_mine_cells_span.ys
read_verilog ../top.v
extract -mine out.ilang -mine_cells_span 3 5
write_verilog synth.v
simple/scripts/extract_mine_limit_matches_per_module.ys → simple/extract/extract_mine_limit_matches_per_module.ys
read_verilog ../top.v
extract -mine out.ilang -mine_limit_matches_per_module 5
write_verilog synth.v
simple/scripts/extract_mine_max_fanout.ys → simple/extract/extract_mine_max_fanout.ys
read_verilog ../top.v
extract -mine out.ilang -mine_max_fanout 2
write_verilog synth.v
simple/scripts/extract_mine_min_freq.ys → simple/extract/extract_mine_min_freq.ys
read_verilog ../top.v
extract -mine out.ilang -mine_min_freq 10
write_verilog synth.v
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment