Update to xilinx INV primitive use

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_asym_ram_sdp_write_wider.ys

@@ -17,8 +17,8 @@ stat
 #Vivado synthesizes 1 RAMB18E1.
 select -assert-count 2 t:BUFG
 select -assert-count 9 t:FDRE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 6 t:LUT3
 select -assert-count 8 t:RAM128X1D
 
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT3 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:INV t:LUT3 t:RAM128X1D %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_1.ys

@@ -8,6 +8,6 @@ equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equ
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristates_1 # Constrain all select calls below inside the top module
 #Vivado synthesizes 3 IBUF, 1 OBUFT.
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 1 t:$_TBUF_
-select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
+select -assert-none t:INV t:$_TBUF_ %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_tristates_2.ys

@@ -8,6 +8,6 @@ equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equ
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristates_2 # Constrain all select calls below inside the top module
 #Vivado synthesizes 3 IBUF, 1 OBUFT.
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 1 t:$_TBUF_
-select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D
+select -assert-none t:INV t:$_TBUF_ %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_no_change.ys

@@ -17,9 +17,9 @@ stat
 #Vivado synthesizes 1 RAMB36E1, 28 FDRE.
 select -assert-count 1 t:BUFG
 select -assert-count 53 t:FDRE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 9 t:LUT2
 select -assert-count 11 t:LUT3
 select -assert-count 16 t:RAM128X1D
 
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:INV t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D

architecture/xilinx_ug901_synthesis_examples/xilinx_ug901_xilinx_ultraram_single_port_read_first.ys

@@ -16,9 +16,9 @@ cd xilinx_ultraram_single_port_read_first
 #Vivado synthesizes 1 RAMB18E1, 28 FDRE.
 select -assert-count 1 t:BUFG
 select -assert-count 53 t:FDRE
-select -assert-count 1 t:LUT1
+select -assert-count 1 t:INV
 select -assert-count 8 t:LUT2
 select -assert-count 11 t:LUT3
 select -assert-count 16 t:RAM128X1D
 
-select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D
+select -assert-none t:BUFG t:FDRE t:INV t:LUT2 t:LUT3 t:RAM128X1D %% t:* %D