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yosys-tests
Commit 6c10ffa6 by Miodrag Milanovic
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Fix gowin according to changes

parent 20dc7354
Showing with 44 additions and 26 deletions
architecture/synth_gowin/synth_gowin.ys
......@@ -5,8 +5,9 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 1 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
select -assert-count 1 t:VCC
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF t:VCC %% t:* %D
architecture/synth_gowin/synth_gowin_nobram.ys
......@@ -14,9 +14,12 @@ cd top
stat
select -assert-count 35 t:DFF
select -assert-count 16 t:IBUF
select -assert-count 6 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 24 t:LUT4
select -assert-count 3 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 64 t:LUT4
select -assert-count 32 t:MUX2_LUT5
select -assert-count 16 t:MUX2_LUT6
select -assert-count 8 t:MUX2_LUT7
select -assert-count 8 t:OBUF
select -assert-count 8 t:RAM16S4
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:OBUF t:RAM16S4 %% t:* %D
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:OBUF t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:RAM16S4 %% t:* %D
architecture/synth_gowin/synth_gowin_nodffe.ys
......@@ -9,10 +9,10 @@ equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:$_DFFE_PP_
select -assert-count 1 t:DFFE
select -assert-count 3 t:IBUF
select -assert-count 1 t:OBUF
select -assert-none t:$_DFFE_PP_ t:IBUF t:OBUF %% t:* %D
select -assert-none t:DFFE t:IBUF t:OBUF %% t:* %D
design -load read
hierarchy -top top
......
architecture/synth_gowin/synth_gowin_nodram.ys
......@@ -17,12 +17,15 @@ cd top
stat
select -assert-count 35 t:DFF
select -assert-count 16 t:IBUF
select -assert-count 6 t:LUT2
select -assert-count 1 t:LUT3
select -assert-count 24 t:LUT4
select -assert-count 3 t:LUT2
select -assert-count 4 t:LUT3
select -assert-count 64 t:LUT4
select -assert-count 32 t:MUX2_LUT5
select -assert-count 16 t:MUX2_LUT6
select -assert-count 8 t:MUX2_LUT7
select -assert-count 8 t:OBUF
select -assert-count 8 t:RAM16S4
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:OBUF t:RAM16S4 %% t:* %D
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:OBUF t:RAM16S4 %% t:* %D
design -load read
hierarchy -top top
......@@ -40,8 +43,10 @@ cd top
stat
select -assert-count 520 t:DFF
select -assert-count 16 t:IBUF
select -assert-count 9 t:LUT2
select -assert-count 622 t:LUT3
select -assert-count 345 t:LUT4
select -assert-count 592 t:LUT3
select -assert-count 987 t:LUT4
select -assert-count 464 t:MUX2_LUT5
select -assert-count 185 t:MUX2_LUT6
select -assert-count 64 t:MUX2_LUT7
select -assert-count 8 t:OBUF
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:OBUF %% t:* %D
select -assert-none t:DFF t:IBUF t:LUT2 t:LUT3 t:LUT4 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:OBUF %% t:* %D
architecture/synth_gowin/synth_gowin_noflatten.ys
......@@ -5,8 +5,10 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -noflatten # equivalency
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 1 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
select -assert-count 1 t:VCC
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF t:VCC %% t:* %D
architecture/synth_gowin/synth_gowin_retime.ys
......@@ -5,8 +5,9 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -retime # equivalency che
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 1 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
select -assert-count 1 t:VCC
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF t:VCC %% t:* %D
architecture/synth_gowin/synth_gowin_run.ys
......@@ -5,8 +5,10 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -run begin:vout # equival
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 1 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
select -assert-count 1 t:VCC
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF t:VCC %% t:* %D
architecture/synth_gowin/synth_gowin_top.ys
......@@ -5,8 +5,10 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -top top # equivalency ch
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 1 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
select -assert-count 1 t:VCC
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF t:VCC %% t:* %D
architecture/synth_gowin/synth_gowin_vout.ys
......@@ -5,8 +5,10 @@ equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -vout vout.v # equivalenc
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 6 t:ALU
select -assert-count 15 t:GND
select -assert-count 1 t:GND
select -assert-count 12 t:IBUF
select -assert-count 8 t:LUT3
select -assert-count 10 t:OBUF
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF %% t:* %D
select -assert-count 1 t:VCC
select -assert-none t:ALU t:GND t:IBUF t:LUT3 t:OBUF t:VCC %% t:* %D
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