Commit 222a2639 by Miodrag Milanovic

use different top model

parent 6ac0f57e
read_verilog -sv ../top.v read_verilog -sv ../top_clean.v
aigmap aigmap
write_aiger -zinit aiger.aiger write_aiger -zinit aiger.aiger
synth -top top synth -top top
......
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