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lvzhengyang
yosys-tests
Commits
222a2639
Commit
222a2639
authored
Jul 17, 2019
by
Miodrag Milanovic
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use different top model
parent
6ac0f57e
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backends/scripts/write_aiger_zinit.ys
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backends/scripts/write_aiger_zinit.ys
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222a2639
read_verilog -sv ../top.v
read_verilog -sv ../top
_clean
.v
aigmap
write_aiger -zinit aiger.aiger
synth -top top
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