Add and update tests in simple and misc groups

Add tests for splitnets command
Expand coverage for trace command
Expand coverage for splice command (tests for options)
Expand coverage for scc command (different loops)
Expand coverage for rename command
Change test for passes/techmap/deminout
Update test for 'dff2dffe -direct' command
Add test for 'dffsr2dff' command
Expand coverage for iopadmap command

misc/Makefile

@@ -30,6 +30,7 @@ $(eval $(call template,torder,torder torder_stop torder_noautostop ))
 
 #trace
 $(eval $(call template,trace,trace ))
+$(eval $(call template,trace_mem,trace_mem ))
 
 #write_file
 $(eval $(call template,write_file,write_file write_file_a ))
@@ -43,6 +44,9 @@ $(eval $(call template,show, show show_colorattr show_colors show_color show_enu
 
 #scc
 $(eval $(call template,scc, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
+$(eval $(call template,scc_feedback, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
+$(eval $(call template,scc_hier_feedback, scc scc_all_cell_types scc_expect scc_max_depth scc_nofeedback scc_select scc_set_attr ))
+
 
 #scatter
 $(eval $(call template,scatter, scatter ))
@@ -140,4 +144,11 @@ $(eval $(call template,sat, sat_dump_cnf sat_dump_json sat_dump_vcd sat_initstep
 $(eval $(call template,sim,sim sim_a sim_clock sim_d sim_n sim_rstlen sim_vcd sim_w sim_zinit ))
 $(eval $(call template,sim_mem,sim sim_a sim_clockn sim_clock_mem sim_d sim_n sim_resetn sim_reset sim_rstlen sim_vcd sim_w sim_zinit_mem ))
 
+#splitnets
+$(eval $(call template,splitnets, splitnets splitnets_format splitnets_ports splitnets_driver splitnets_dpf ))
+$(eval $(call template,splitnets_logic, splitnets splitnets_format splitnets_ports splitnets_driver splitnets_dpf ))
+
+#splice
+$(eval $(call template,splice, splice splice_sel_by_cell splice_sel_by_wire splice_sel_any_bit splice_wires splice_no_outputs splice_port splice_no_port ))
+
 .PHONY: all clean

misc/scc_feedback/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o_mid,o_rtl;
+
+always @(posedge cin)
+	A <= o_mid;
+
+assign o_mid = x & o_rtl;
+assign o_rtl = y & o_mid;
+
+endmodule

misc/scc_hier_feedback/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o_mid,o_rtl;
+
+always @(posedge cin)
+	A <= o_mid;
+
+middle u_mid (.x(x),.y(o_rtl),.o(o_mid));
+u_rtl inst_u_rtl (.x(o_mid),.y(y),.o(o_rtl));
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+wire o1,o2;
+
+assign o1 = x & o2;
+assign o2 = y & o1;
+assign o = o1;
+endmodule
+
+module u_rtl
+(
+	input x,
+	input y,
+	output o
+);
+
+
+wire o1,o2;
+
+assign o1 = x & o2;
+assign o2 = y & o1;
+assign o = o1;
+endmodule

misc/scripts/rename_wire.ys

 read_verilog ../top.v
 proc
-tee -o result.log rename -wire middle mid_module
+tee -o result.log rename -wire o mid_o

misc/scripts/scc.ys

 read_verilog ../top.v
 proc
 tee -o result.log scc top
+synth
+tee -o result.log scc top

misc/scripts/splice.ys

+read_verilog ../top.v
+tee -o result.log splice
+proc
+tee -o result.log splice
+synth
+tee -o result.log splice

misc/scripts/splice_no_outputs.ys

+read_verilog ../top.v
+synth
+tee -o result.log splice -no_outputs

misc/scripts/splice_no_port.ys

+read_verilog ../top.v
+synth
+tee -o result.log splice -no_port q_b

misc/scripts/splice_port.ys

+read_verilog ../top.v
+synth
+tee -o result.log splice -port q_b

misc/scripts/splice_sel_any_bit.ys

+read_verilog ../top.v
+synth
+tee -o result.log splice -sel_any_bit

misc/scripts/splice_sel_by_cell.ys

+read_verilog ../top.v
+synth
+tee -o result.log splice -sel_by_cell

misc/scripts/splice_sel_by_wire.ys

+read_verilog ../top.v
+synth
+tee -o result.log splice -sel_by_wire

misc/scripts/splice_wires.ys

+read_verilog ../top.v
+synth
+tee -o result.log splice -wires

misc/scripts/splitnets.ys

+read_verilog -sv ../top.v
+tee -o result.log splitnets

misc/scripts/splitnets_dpf.ys

+read_verilog -sv ../top.v
+tee -o result.log splitnets -driver -ports -format www

misc/scripts/splitnets_driver.ys

+read_verilog -sv ../top.v
+tee -o result.log splitnets -driver

misc/scripts/splitnets_format.ys

+read_verilog -sv ../top.v
+tee -o result.log splitnets -format ()

misc/scripts/splitnets_ports.ys

+read_verilog -sv ../top.v
+tee -o result.log splitnets -ports

misc/scripts/trace.ys

 read_verilog ../top.v
 tee -o result.log trace synth -top top
+proc
+tee -o result.log trace synth -top top
+synth
+tee -o result.log trace synth -top top

misc/scripts/trace_mem.ys

+read_verilog ../top.v
+tee -o result.log trace synth -top top
+proc
+memory
+tee -o result.log trace synth -top top
+synth
+tee -o result.log trace synth -top top

misc/splice/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

misc/splitnets/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

misc/splitnets_logic/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output reg cout
+ );
+
+ reg ASSERT = 1;
+ (* anyconst *) reg foo;
+ (* anyseq *) reg too;
+
+
+
+ initial begin
+    begin
+        A = 0;
+        cout = 0;
+    end
+ end
+
+`ifndef BUG
+always @(posedge x) begin
+    if ($initstate)
+        A <= 0;
+    A <=  y + cin + too;
+    assume(too);
+    assume(s_eventually too);
+end
+always @(negedge x) begin
+    if ($initstate)
+        cout <= 0;
+        cout <=  y + A + foo;
+    assert(ASSERT);
+    assert(s_eventually ASSERT);
+end
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule

misc/trace_mem/top.v

+module top
+(
+	input [7:0] data_a, data_b,
+	input [6:1] addr_a, addr_b,
+	input we_a, we_b, re_a, re_b, clka, clkb,
+	output reg [7:0] q_a, q_b
+);
+	// Declare the RAM variable
+	reg [7:0] ram[63:0];
+	
+	initial begin
+        q_a <= 8'h00;        
+        q_b <= 8'd0;
+	end
+	
+	// Port A
+	always @ (posedge clka)
+	begin
+`ifndef BUG        
+		if (we_a) 
+`else        
+		if (we_b) 
+`endif
+		begin
+			ram[addr_a] <= data_a;
+			q_a <= data_a;
+		end
+		if (re_b) 
+		begin
+			q_a <= ram[addr_a];
+		end
+	end
+	
+	// Port B
+	always @ (posedge clkb)
+	begin
+`ifndef BUG        
+		if (we_b) 
+`else        
+		if (we_a) 
+`endif
+		begin
+			ram[addr_b] <= data_b;
+			q_b <= data_b;
+		end
+		if (re_b)
+		begin
+			q_b <= ram[addr_b];
+		end
+	end
+	
+endmodule								 

simple/Makefile

@@ -38,8 +38,8 @@ $(eval $(call template,tristate_const_1, tristate))
 $(eval $(call template,tristate_const_data, tristate))
 
 # Demoting I/O port
-$(eval $(call template,inout_port, tristate))
-$(eval $(call template,inout_port_demote, tristate))
+$(eval $(call template,inout_port, deminout deminout_synth))
+$(eval $(call template,inout_port_demote, deminout deminout_synth))
 
 # MACC cells
 $(eval $(call template,macc, macc))
@@ -88,11 +88,14 @@ $(eval $(call template,attrmap,attrmap attrmap_modattr))
 
 #dff2dffe -unmap
 # dff2dffe_unmap_direct - skipped: ERROR: Found error in internal cell \dffe.$procdff$47 ($dffe) at
-$(eval $(call template,dff2dffe_unmap,dff2dffe_unmap dff2dffe_unmap_mince))
+$(eval $(call template,dff2dffe_unmap,dff2dffe_unmap dff2dffe_unmap_mince dff2dffe_unmap_direct))
 
 #dff2dffs
 $(eval $(call template,dff2dffs,dff2dffs))
 
+#dffsr2dff
+$(eval $(call template,dffsr2dff,dffsr2dff))
+
 #extract
 $(eval $(call template,extract,extract_cell_attr extract_compat extract_constports extract_map_design extract_ignore_parameters extract_ignore_param  extract_map extract_mine_cells_span extract_mine_limit_matches_per_module extract_mine_max_fanout extract_mine_min_freq extract_mine_split extract_mine extract_nodefaultswaps extract_perm extract_swap extract_verbose extract_wire_attr ))
 
@@ -118,5 +121,8 @@ $(eval $(call template,flowmap,flowmap flowmap_cells flowmap_debug_relax flowmap
 $(eval $(call template,flowmap_latch,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax  flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
 $(eval $(call template,flowmap_mem,flowmap flowmap_cells flowmap_debug_relax flowmap_debug flowmap_maxlut flowmap_minlut flowmap_optarea flowmap_r_alpha flowmap_r_beta flowmap_r_gamma flowmap_relax flowmap_relax_debug flowmap_relax_debug_relax flowmap_top))
 
+#iopadmap
+$(eval $(call template,iopadmap,iopadmap))
+
 
 .PHONY: all clean

simple/dffsr2dff/testbench.v

+module testbench;
+    reg clk;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 clk = 0;
+        repeat (10000) begin
+            #5 clk = 1;
+            #5 clk = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire doutB;
+
+    top uut (
+        .clk (clk ),
+        .a (dinA ),
+        .b (doutB )
+    );
+    
+    always @(posedge clk) begin
+    #3;
+    dinA <= !dinA;
+    end
+    
+	assert_dff ff_test(.clk(clk), .test(doutB), .pat(1'b1));
+    
+endmodule

simple/dffsr2dff/top.v

+module dffsr
+    ( input d, clk, pre, clr, output reg q );
+	always @( posedge clk, posedge pre, negedge clr )
+		if ( pre )
+			q <= 1'b1;
+		else if ( clr )
+			q <= 1'b0;
+		else
+            q <= d;
+endmodule
+
+module top (
+input clk,
+input a,
+output b
+);
+
+dffsr u_dffsr (
+        .clk (clk ),
+`ifndef BUG
+        .clr (1'b1),
+        .pre (1'b1),
+`else
+        .clr (1'b0),
+        .pre (1'b0),
+`endif
+        .d (a ),
+        .q (b )
+    );
+
+endmodule

simple/iopadmap/testbench.v

+module testbench;
+    reg en;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 en = 0;
+        repeat (10000) begin
+            #5 en = 1;
+            #5 en = 0;
+        end
+
+        $display("OKAY");    
+    end
+   
+    
+    reg dinA = 0;
+    wire [1:0] dioB;    
+    wire [1:0] doutC;
+
+    top uut (
+        .en (en ),
+        .a (dinA ),
+        .b (dioB ),
+        .c (doutC )
+    );
+    
+    always @(posedge en) begin
+    #3;
+    dinA <= !dinA;
+    end
+	
+	assert_dff b_test(.clk(en), .test(dinA), .pat(dioB[0]));
+	
+	assert_dff c_test(.clk(en), .test(dinA), .pat(doutC[0]));
+	
+	assert_dff cz_test(.clk(!en), .test(1'bZ), .pat(doutC[0]));
+    
+endmodule
+

simple/iopadmap/top.v

+module tristate (en, i, io, o);
+    input en;
+    input i;
+    inout [1:0] io;
+    output [1:0] o;
+
+    reg [1:0] io_buf;
+    assign io = io_buf;
+
+`ifndef BUG
+    always @(en or i)
+		io_buf[0] <= (en)? i : 1'bZ;
+
+    always @(en or i)
+		io_buf[1] <= (i)? en : 1'bZ;
+
+    assign o = (en)? io : 2'bZZ;
+`else
+	always @(en or i)
+		io_buf[0] <= (en)? ~i : 1'bZ;
+
+    always @(en or i)
+		io_buf[1] <= (i)? ~en : 1'bZ;
+
+    assign o = (en)? ~io : 2'bZZ;
+`endif
+endmodule
+
+
+module top (
+input en,
+input a,
+inout [1:0] b,
+output [1:0] c
+);
+
+tristate u_tri (
+        .en (en ),
+        .i (a ),
+        .io (b ),
+        .o (c )
+    );
+
+endmodule

simple/scripts/deminout.ys

+read_verilog ../top.v
+deminout
+write_verilog synth.v

simple/scripts/deminout_synth.ys

+read_verilog ../top.v
+synth -top top
+deminout
+write_verilog synth.v

simple/scripts/dff2dffe_unmap_direct.ys

 read_verilog ../top.v
 proc
+dff2dffe
 dff2dffe -direct $dff $dffe
 dff2dffe -unmap
 synth -top top
-dff2dffe -direct $dff $dffe
+dff2dffe -direct $_DFF_P_ $_DFFE_PP_
 dff2dffe -unmap
 flatten
 opt

simple/scripts/dffsr2dff.ys

+read_verilog ../top.v
+proc
+dffsr2dff
+techmap
+dffsr2dff
+design -reset
+read_verilog ../top.v
+synth -top top
+dffsr2dff
+flatten
+opt
+opt_rmdff
+dffsr2dff
+write_verilog synth.v

simple/scripts/iopadmap.ys

+read_verilog ../top.v
+proc
+iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
+iopadmap -widthparam wp -nameparam np -bits -inpad IBUF O:I -outpad IOBUFE O:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE O:IO -tinoutpad IOBUFE O:IO
+design -reset
+read_verilog ../top.v
+proc
+write_verilog synth.v