Add new tests to 'backends'

backends/Makefile

@@ -38,7 +38,7 @@ $(eval $(call template,write_btor_shiftx,write_btor write_btor_v write_btor_s))
 $(eval $(call template,write_edif,write_edif write_edif_top write_edif_nogndvcc write_edif_pvector_par write_edif_pvector_bra write_edif_pvector_ang write_edif_attrprop ))
 
 #write_firrtl
-$(eval $(call template,write_firrtl,write_firrtl write_firrtl))
+$(eval $(call template,write_firrtl,write_firrtl))
 #write_firrtl_mem_wr - issue #938
 #terminate called after throwing an instance of 'std::out_of_range'
 #  what():  dict::at()
@@ -48,6 +48,7 @@ $(eval $(call template,write_firrtl_logic,write_firrtl ))
 $(eval $(call template,write_firrtl_reduce,write_firrtl ))
 $(eval $(call template,write_firrtl_shift,write_firrtl ))
 $(eval $(call template,write_firrtl_shiftx,write_firrtl ))
+$(eval $(call template,write_firrtl_paramod,write_firrtl))
 
 #write_ilang
 $(eval $(call template,write_ilang,write_ilang write_ilang_selected))

backends/scripts/write_firrtl.ys

 read_verilog ../top.v
 proc
 write_firrtl firrtl.firrtl
-write_verilog synth.v 
+synth
+write_firrtl firrtl2.firrtl
+write_verilog synth.v

backends/write_edif/top.v

@@ -7,7 +7,9 @@ module top
  output reg A,
  output reg cout
  );
- 
+
+ wire bb_out;
+
  initial begin
     A = 0;
     cout = 0;
@@ -24,12 +26,16 @@ end
 assign {cout,A} =  cin - y * x;
 `endif
 
-bb ubb (cin,y,x);
+bb ubb (cin,y,x,bb_out);
 
 endmodule
 
-(* black_box *) module bb(in1, in2, clk);
+(* black_box *) module bb(in1, in2, clk, out1);
  input in1;
  input in2;
  input clk;
+  output reg out1;
+
+ always @(posedge clk)
+	out1 <= in1 & in2;
 endmodule

backends/write_firrtl_paramod/testbench.v

+module middle_tb
+(
+	input x,
+	input y,
+	output o
+);
+
+parameter Y = 1'b1;
+
+urtl_tb u_urtl (.x(x),.o(o),.y(Y));
+endmodule
+
+module urtl_tb
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule
+
+module testbench;
+    reg [0:2] in;
+
+	reg patt_A = 1'bX;
+	wire patt_cout;
+	wire cout,o;
+    wire A;
+
+    initial begin
+        // $dumpfile("testbench.vcd");
+        // $dumpvars(0, testbench);
+
+        #5 in = 0;
+        repeat (10000) begin
+            #5 in = in + 1;
+        end
+
+        $display("OKAY");
+    end
+
+    top uut (
+	.x(in[0]),
+	.y(in[1]),
+	.cin(in[2]),
+	.A(A),
+	.cout(cout)
+	);
+
+	always @(posedge in[2])
+	patt_A <= o;
+
+assign pattcout =  in[2]? in[1] : in[0];
+
+middle_tb #(1'b0) u_mid1 (.x(in[0]),.o(o),.y(1'b0));
+middle_tb #(1'b0) u_mid2 (.x(in[0]),.o(o),.y(1'b1));
+middle_tb #(1'b0) u_mid3 (.x(in[0]),.o(o),.y(1'bX));
+middle_tb #(1'b0) u_mid4 (.x(in[0]),.o(o),.y(1'bX));
+
+	assert_comb out_test(.A(patt_A), .B(A));
+
+endmodule

backends/write_firrtl_paramod/top.v

+module top
+(
+ input x,
+ input y,
+ input cin,
+
+ output reg A,
+ output cout
+ );
+ parameter X = 1;
+ wire o;
+
+`ifndef BUG
+always @(posedge cin)
+	A <= o;
+
+assign cout =  cin? y : x;
+
+middle #(1'b0) u_mid1 (.x(x),.o(o),.y(1'b0));
+middle #(1'b0) u_mid2 (.x(x),.o(o),.y(1'b1));
+middle #(1'b0) u_mid3 (.x(x),.o(o),.y(1'bX));
+middle #(1'b0) u_mid4 (.x(x),.o(o),.y(1'bX));
+`else
+assign {cout,A} =  cin - y * x;
+`endif
+
+endmodule
+
+module middle
+(
+	input x,
+	input y,
+	output o
+);
+
+parameter Y = 1'b1;
+
+urtl u_urtl (.x(x),.o(o),.y(Y));
+endmodule
+
+module urtl
+(
+	input x,
+	input y,
+	output o
+);
+
+assign o = x + y;
+endmodule