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lvzhengyang
yosys-tests
Commits
1c2dc065
Commit
1c2dc065
authored
Sep 23, 2019
by
Eddie Hung
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Run all hand-generated testcases, not just those mul_*.v
parent
b016dd37
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architecture/synth_xilinx_dsp/run-test.sh
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architecture/synth_xilinx_dsp/run-test.sh
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1c2dc065
...
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@@ -29,7 +29,7 @@ EXTRA_FLAGS="\
-l ../../../../../techlibs/xilinx/cells_sim.v"
cp ../
*
.v
.
${
MAKE
:-
make
}
-f
../../../../tools/autotest.mk
$seed
mul_
*
.v
EXTRA_FLAGS
=
"
$EXTRA_FLAGS
"
${
MAKE
:-
make
}
-f
../../../../tools/autotest.mk
$seed
*
.v
EXTRA_FLAGS
=
"
$EXTRA_FLAGS
"
cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
cp ~/yosys/yosys-bench/verilog/benchmarks_small/macc/common.py common_macc.py
...
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