Update synth_xilinx_dsp tests

architecture/synth_xilinx_dsp/generate_muladd.py

+#!/usr/bin/env python3
+
+from common_muladd import gen_muladd
+
+ARange = ['24','24s','25','25s','36','36s']
+BRange = ['17','17s','18','18s','19','19s']
+CRange = ['32','32s','40','40s','48','48s']
+
+if __name__ == "__main__":
+    gen_muladd(ARange, BRange, CRange, reg="ABMP")

architecture/synth_xilinx_dsp/mul_25s_18s_keepABP_.v

@@ -23,7 +23,7 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd mul_25s_18s_keepABP_; select t:DSP48E1 -assert-count 1; select t:FD* -assert-count 86";
+    wire [4095:0] assert_area = "cd mul_25s_18s_keepABP_; select t:DSP48E1 -assert-count 1; select t:FD* -assert-count 43";
 endmodule
 `endif
 

architecture/synth_xilinx_dsp/run-test.sh

@@ -19,18 +19,26 @@ if ! which iverilog > /dev/null ; then
 fi
 
 #wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/generate.py -O generate_mul.py -o /dev/null
-cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
-PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
-cp ~/yosys/yosys-bench/verilog/benchmarks_small/macc/common.py common_macc.py
-PYTHONPATH=".:$PYTHONPATH" python3 ../generate_macc.py
-cp ~/yosys/yosys-bench/verilog/benchmarks_small/muladd/common.py common_muladd.py
-PYTHONPATH=".:$PYTHONPATH" python3 ../generate_muladd.py
-python3 ../assert_area.py
-cp ../*.v .
-${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
+
+EXTRA_FLAGS="\
     -p 'design -copy-to __test __test; \
         synth_xilinx; \
         design -copy-from __test *; \
         select -assert-any __test; \
         script -scriptwire __test/w:assert_area'\
     -l ../../../../../techlibs/xilinx/cells_sim.v"
+
+cp ../*.v .
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed mul_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
+
+cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
+cp ~/yosys/yosys-bench/verilog/benchmarks_small/macc/common.py common_macc.py
+cp ~/yosys/yosys-bench/verilog/benchmarks_small/muladd/common.py common_muladd.py
+PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
+PYTHONPATH=".:$PYTHONPATH" python3 ../generate_macc.py
+PYTHONPATH=".:$PYTHONPATH" python3 ../generate_muladd.py
+python3 ../assert_area.py
+
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed mul_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed macc_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
+${MAKE:-make} -f ../../../../tools/autotest.mk $seed muladd_*.v EXTRA_FLAGS="$EXTRA_FLAGS"