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yosys-tests
Commit 1c2dc065 by Eddie Hung
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Run all hand-generated testcases, not just those mul_*.v

parent b016dd37
Showing with 1 additions and 1 deletions
architecture/synth_xilinx_dsp/run-test.sh
......@@ -29,7 +29,7 @@ EXTRA_FLAGS="\
-l ../../../../../techlibs/xilinx/cells_sim.v"
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed mul_*.v EXTRA_FLAGS="$EXTRA_FLAGS"
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="$EXTRA_FLAGS"
cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
cp ~/yosys/yosys-bench/verilog/benchmarks_small/macc/common.py common_macc.py
......
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