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yosys-tests
Unverified Commit 13009106 by Miodrag Milanović Committed by GitHub
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Merge pull request #75 from SergeyDegtyar/test_changes_in_yosys-test_3 

The third variant of changes in yosys-tests
parents e9bff780 a965148e
Showing with 862 additions and 4582 deletions
regression/Makefile
......@@ -17,9 +17,6 @@ clean::
))
endef
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00018
$(eval $(call template,issue_00018,issue_00018))
......@@ -30,9 +27,7 @@ $(eval $(call template,issue_00041,issue_00041))
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,issue_00065,issue_00065))
endif
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
......@@ -52,7 +47,7 @@ $(eval $(call template,issue_00081,issue_00081))
#Parsing Verilog input from `top_fault.v' to AST representation.
#top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
#
$(eval $(call template,issue_00082,issue_00082))
$(eval $(call template,issue_00082,issue_00082_fail))
#issue_00083
#Warning: Deep recursion in AST simplifier.
......@@ -60,7 +55,7 @@ $(eval $(call template,issue_00082,issue_00082))
#run.sh: line 21: 17264 Segmentation fault (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
#make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
#
$(eval $(call template,issue_00083,issue_00083))
$(eval $(call template,issue_00083,issue_00083_fail))
#issue_00084
$(eval $(call template,issue_00084,issue_00084))
......@@ -75,25 +70,25 @@ $(eval $(call template,issue_00086,issue_00086))
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
$(eval $(call template,issue_00089,issue_00089))
$(eval $(call template,issue_00089,issue_00089_fail))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
$(eval $(call template,issue_00093,issue_00093))
$(eval $(call template,issue_00093,issue_00093_fail))
#issue_00095
$(eval $(call template,issue_00095,issue_00095))
$(eval $(call template,issue_00095,issue_00095_fail))
#issue_00096
$(eval $(call template,issue_00096,issue_00096))
$(eval $(call template,issue_00096,issue_00096_fail))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
#issue_00099
$(eval $(call template,issue_00099,issue_00099))
$(eval $(call template,issue_00099,issue_00099_fail))
#issue_00102
$(eval $(call template,issue_00102,issue_00102))
......@@ -150,7 +145,7 @@ $(eval $(call template,issue_00194,issue_00194))
$(eval $(call template,issue_00195,issue_00195))
#issue_00196
$(eval $(call template,issue_00196,issue_00196))
$(eval $(call template,issue_00196,issue_00196_fail))
#issue_00210
$(eval $(call template,issue_00210,issue_00210))
......@@ -201,7 +196,7 @@ $(eval $(call template,issue_00350,issue_00350))
$(eval $(call template,issue_00361,issue_00361))
#issue_00362
$(eval $(call template,issue_00362,issue_00362))
$(eval $(call template,issue_00362,issue_00362_fail))
#issue_00372
$(eval $(call template,issue_00372,issue_00372))
......@@ -240,16 +235,16 @@ $(eval $(call template,issue_00527,issue_00527))
$(eval $(call template,issue_00567,issue_00567))
#issue_00582
$(eval $(call template,issue_00582,issue_00582))
$(eval $(call template,issue_00582,issue_00582_fail))
#issue_00589
$(eval $(call template,issue_00589,issue_00589))
#issue_00594
$(eval $(call template,issue_00594,issue_00594))
$(eval $(call template,issue_00594,issue_00594_fail))
#issue_00603
$(eval $(call template,issue_00603,issue_00603))
$(eval $(call template,issue_00603,issue_00603_fail))
#issue_00628
$(eval $(call template,issue_00628,issue_00628))
......@@ -258,10 +253,10 @@ $(eval $(call template,issue_00628,issue_00628))
$(eval $(call template,issue_00630,issue_00630))
#issue_00635
$(eval $(call template,issue_00635,issue_00635))
$(eval $(call template,issue_00635,issue_00635_fail))
#issue_00639
$(eval $(call template,issue_00639,issue_00639))
$(eval $(call template,issue_00639,issue_00639_fail))
#issue_00642
$(eval $(call template,issue_00642,issue_00642))
......@@ -294,7 +289,7 @@ $(eval $(call template,issue_00708,issue_00708))
$(eval $(call template,issue_00737,issue_00737))
#issue_00763
$(eval $(call template,issue_00763,issue_00763))
$(eval $(call template,issue_00763,issue_00763_fail))
#issue_00767
$(eval $(call template,issue_00767,issue_00767))
......@@ -310,6 +305,9 @@ $(eval $(call template,issue_00781,issue_00781))
#issue_00785
$(eval $(call template,issue_00785,issue_00785))
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00807
$(eval $(call template,issue_00807,issue_00807))
......@@ -320,7 +318,7 @@ $(eval $(call template,issue_00809,issue_00809))
$(eval $(call template,issue_00810,issue_00810))
#issue_00814
$(eval $(call template,issue_00814,issue_00814))
$(eval $(call template,issue_00814,issue_00814_fail))
#issue_00823
$(eval $(call template,issue_00823,issue_00823))
......@@ -340,7 +338,7 @@ $(eval $(call template,issue_00857,issue_00857))
#issue_00862
$(eval $(call template,issue_00862,issue_00862))
#issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
#issue_00865
$(eval $(call template,issue_00865,issue_00865))
#issue_00867
......@@ -409,6 +407,9 @@ $(eval $(call template,issue_00997,issue_00997))
#issue_01002
$(eval $(call template,issue_01002,issue_01002))
#issue_01014
$(eval $(call template,issue_01014,issue_01014))
#issue_01016
$(eval $(call template,issue_01016,issue_01016))
......@@ -431,7 +432,7 @@ $(eval $(call template,issue_01040,issue_01040))
$(eval $(call template,issue_01047,issue_01047))
#issue_01063
$(eval $(call template,issue_01063,issue_01063))
$(eval $(call template,issue_01063,issue_01063_fail))
#issue_01065
$(eval $(call template,issue_01065,issue_01065))
......@@ -446,7 +447,7 @@ $(eval $(call template,issue_01084,issue_01084))
$(eval $(call template,issue_01091,issue_01091))
#issue_01093
$(eval $(call template,issue_01093,issue_01093))
$(eval $(call template,issue_01093,issue_01093_fail))
#issue_01115
$(eval $(call template,issue_01115,issue_01115))
......@@ -458,7 +459,7 @@ $(eval $(call template,issue_01118,issue_01118))
$(eval $(call template,issue_01128,issue_01128))
#issue_01131
$(eval $(call template,issue_01131,issue_01131))
$(eval $(call template,issue_01131,issue_01131_fail))
#issue_01132
$(eval $(call template,issue_01132,issue_01132))
......@@ -467,7 +468,7 @@ $(eval $(call template,issue_01132,issue_01132))
$(eval $(call template,issue_01135,issue_01135))
#issue_01144
$(eval $(call template,issue_01144,issue_01144))
$(eval $(call template,issue_01144,issue_01144_fail))
#issue_01145
$(eval $(call template,issue_01145,issue_01145))
......@@ -500,8 +501,6 @@ $(eval $(call template,issue_01364,issue_01364))
$(eval $(call template,issue_01372,issue_01372))
#Still open bugs (should be failed):
#issue_00329
$(eval $(call template,issue_00329,issue_00329))
......@@ -512,9 +511,6 @@ $(eval $(call template,issue_00623,issue_00623))
#issue_00656
$(eval $(call template,issue_00656,issue_00656))
#issue_01014
$(eval $(call template,issue_01014,issue_01014))
#issue_01126
$(eval $(call template,issue_01126,issue_01126))
......@@ -545,7 +541,4 @@ $(eval $(call template,issue_01291,issue_01291))
#issue_01360
$(eval $(call template,issue_01360,issue_01360))
.PHONY: all clean
regression/issue_00018/issue_00018.ys 0 → 100644
read_verilog ../top.v
synth -top d
regression/issue_00018/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00018/top.v
......@@ -4,41 +4,116 @@
`timescale 1ns/10ps
module top (
x,clk,rst,a
module d (
cos_z0,
sin_z0,
done,
z0,
start,
clock,
reset
);
// Sine and cosine computer.
//
// This module computes the sine and cosine of an input angle. The
// floating point numbers are represented as integers by scaling them
// up with a factor corresponding to the number of bits after the point.
//
// Ports:
// -----
// cos_z0: cosine of the input angle
// sin_z0: sine of the input angle
// done: output flag indicated completion of the computation
// z0: input angle
// start: input that starts the computation on a posedge
// clock: clock input
// reset: reset input
output x;
reg x;
input clk;
input rst;
input [1:0] a;
output signed [19:0] cos_z0;
reg signed [19:0] cos_z0;
output signed [19:0] sin_z0;
reg signed [19:0] sin_z0;
output done;
reg done;
input signed [19:0] z0;
input start;
input clock;
input reset;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR
reg [5-1:0] i;
reg [1-1:0] state;
reg signed [20-1:0] dz;
reg signed [20-1:0] dx;
reg signed [20-1:0] dy;
reg signed [20-1:0] y;
reg signed [20-1:0] x;
reg signed [20-1:0] z;
if (reset) begin
state = 1'b0;
cos_z0 <= 1;
sin_z0 <= 0;
done <= 1'b0;
x = 0;
y = 0;
z = 0;
i = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
case (state)
1'b0: begin
if (start) begin
x = 159188;
y = 0;
z = z0;
i = 0;
done <= 1'b0;
state = 1'b1;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
1'b1: begin
dx = $signed(y >>> $signed({1'b0, i}));
dy = $signed(x >>> $signed({1'b0, i}));
case (i)
0: dz = 205887;
1: dz = 121542;
2: dz = 64220;
3: dz = 32599;
4: dz = 16363;
5: dz = 8189;
6: dz = 4096;
7: dz = 2048;
8: dz = 1024;
9: dz = 512;
10: dz = 256;
11: dz = 128;
12: dz = 64;
13: dz = 32;
14: dz = 16;
15: dz = 8;
16: dz = 4;
17: dz = 2;
default: dz = 1;
endcase
if ((z >= 0)) begin
x = x - dx;
y = y + dy;
z = z - dz;
end
2'b11: begin
i = 0;
else begin
x = x + dx;
y = y - dy;
z = z + dz;
end
if ((i == (19 - 1))) begin
cos_z0 <= x;
sin_z0 <= y;
state = 1'b0;
done <= 1'b1;
end
else begin
i = i + 1;
end
default: begin
x = 0;
i = 0;
end
endcase
end
......
regression/issue_00041/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/scripts/issue_00059.ys → regression/issue_00059/issue_00059.ys
read_verilog ../top.v
#Myname: added some comment with a colon
synth -top top
write_verilog synth.v
regression/issue_00059/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00065/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00067/issue_00067.ys 0 → 100644
read_verilog ../top.v
freduce
regression/issue_00067/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00067/top.v
module top(b,c);
input b;
output c;
assign c = b;
module test(input en, output reg y);
always @*
y = en & !y;
endmodule
regression/issue_00067/top_fault.v deleted 100644 → 0
module top(input en, output reg y);
always @*
y = en & !y;
endmodule
regression/issue_00071/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00071/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
reg [31:0] reg_32 = 32'bX;
endmodule
regression/issue_00071/top_fault.v deleted 100644 → 0
module top(b);
input b;
reg [31:0] reg_32 = 32'bX;
endmodule
regression/issue_00078/issue_00078.pat 0 → 100644
\\\X\[0\] , \\\X\[1\] , \\\X\[2\] ,
regression/scripts/issue_00078.ys → regression/issue_00078/issue_00078.ys
read_verilog ../top.v
hierarchy
splitnets -ports
write_verilog synth.v
write_verilog result.out
regression/issue_00078/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00078/top.v
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00078/top_fault.v deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/scripts/issue_00781.ys → regression/issue_00081/issue_00081.ys
read_verilog ../top.v
tee -o result.log synth_ice40 -blif test.blif
regression/issue_00081/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00081/top.v
module top(b,c);
input b;
output c;
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
assign c = b;
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
endmodule
module demo_002(y0, y1, y2, y3);
output [63:0] y0, y1, y2, y3;
assign y0 = 1'b_ >= (-1 * -1.17);
assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
assign y3 = 1 ? -1 : 'd0;
endmodule
regression/issue_00081/top_fault.v deleted 100644 → 0
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
endmodule
module demo_002(y0, y1, y2, y3);
output [63:0] y0, y1, y2, y3;
assign y0 = 1'b_ >= (-1 * -1.17);
assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
assign y3 = 1 ? -1 : 'd0;
endmodule
regression/issue_00082/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00082/top.v
module top(b);
module a(b);
input b;
reg c;
task a(b);
endmodule
regression/issue_00082/top_fault.v deleted 100644 → 0
module a(b);
input b;
reg c;
task a(b);
endmodule
regression/issue_00083/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00083/top.v
module top(b);
module a(b);
input b;
reg c;parameter
signed b=b;
endmodule
regression/issue_00083/top_fault.v deleted 100644 → 0
module a(b);
input b;
reg c;parameter
signed b=b;
endmodule
regression/issue_00084/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [9:0] addr = 0;
reg ce = 0;
wire [7:0] q;
top uut (
.clk(clk),
.addr(addr),
.ce(ce),
.q(q)
);
always @(posedge clk) begin
addr <= addr + 1;
end
always @(posedge clk) begin
#3;
ce <= !ce;
end
uut_mem_checker q_test(.clk(clk), .en(ce), .A(q));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'b00000000)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00085/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00085/top.v
module top(b,c);
input b;
output c;
assign c = b;
module a;assign a = 0'sh0;
endmodule
regression/issue_00085/top_fault.v deleted 100644 → 0
module a;assign a = 0'sh0;
endmodule
regression/issue_00086/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00086/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
reg N=0.0/0'H0;
endmodule
regression/issue_00086/top_fault.v deleted 100644 → 0
module top(b);
input b;
reg N=0.0/0'H0;
endmodule
regression/issue_00088/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00089/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00091/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00093/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00095/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00096/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00098/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
always @(clk)
a <= a + 1;
top uut (
.a (a),
.z (z)
);
assert_Z check_output(clk,z[0]);
endmodule
regression/issue_00098/top.v
module top(a,z);
module bug_mika(a,z);
input [7:0] a;
output [7:0] z;
parameter pos = 1;
......
regression/issue_00099/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
wire o1,o2,o3;
always @(clk)
a <= a + 1;
top uut (
.in (a),
.out (z),
.out1 (o1),
.out2 (o2),
.out3 (o3)
);
assert_Z check_output1(clk,o1);
assert_Z check_output2(clk,o2);
assert_Z check_output3(clk,o3);
endmodule
regression/issue_00099/top.v
module top(in, out, out1, out2, out3);
module task_func_test04(in, output, out1, out2, out3);
input [7:0] in;
output [7:0] out;
output [7:0] output;
output out1;
output out2;
output out3;
......
regression/issue_00102/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [35:0] b;
top uut (
.a (clk),
.b (b)
);
assert_Z check_output1(clk,b[0]);
endmodule
regression/issue_00102/top.v
module top (
module test (
a, b
);
input a;
output [35:0] b;
output [1535:0] b;
reg [35:0] G;
reg [1535:0] G;
reg F;
reg H;
reg I;
......@@ -17,8 +17,8 @@ module top (
assign b = muxer(G, {L , H , F , M, J , I}, K, 24, 0);
function [35:0] muxer;
input [35:0] vector;
function [1535:0] muxer;
input [1535:0] vector;
input [23:0] slice;
input [5:0] index;
input size;
......@@ -26,7 +26,7 @@ module top (
input offset;
integer offset;
integer i;
reg [35:0] muxed_value;
reg [1535:0] muxed_value;
begin
muxed_value = vector;
for (i = 0; i < 24; i = i+1)
......
regression/scripts/issue_00111.ys → regression/issue_00111/issue_00111.ys
......@@ -2,7 +2,3 @@ read_verilog ../top.v
synth -top top
splitnets -ports
hierarchy -check
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/issue_00111/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [127:0] state,key = 0;
wire [127:0] out;
/*always @(posedge clk)
begin
state = state + 2300;
key = key + 2500;
end*/
top uut (
.state (state ),
.key (key ),
.out (out )
);
/*genvar index;
generate
for (index=0; index < 128; index=index+25)
begin: gen_code_label
assert_Z check_output(clk,out[index]);
end
endgenerate*/
assert_Z check_output(clk,out[0]);
endmodule
regression/issue_00114/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.clock (clk )
);
endmodule
regression/issue_00114/top.v
module top(
input wire clock
module TestCase(
input wire clock,
);
localparam COUNT = 1600;
......
regression/issue_00126/issue_00126.ys 0 → 100644
read_verilog ../top.v
hierarchy -top test
write_verilog -noexpr -norename result.out
regression/issue_00126/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
always @(posedge clk)
in = in + 1;
top uut (
.in_a(in),
.out_vt(out)
);
endmodule
regression/issue_00126/top.v
module top (in_a, out_vt);
module test (in_a, out_vt);
input [1:0] in_a;
output out_vt;
reg [2:0] result;
assign out_vt = result;
always @(*)
begin
result = 3'b000;
case (in_a)
2'b00 : begin
result = 3'b101;
......@@ -17,8 +21,7 @@ always @(*)
result = 3'b001;
end
default;
default result = 3'b011;
endcase
end
endmodule
regression/issue_00128/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/scripts/issue_00132.ys → regression/issue_00132/issue_00132.ys
read_verilog -defer ../top.v
chparam -set incr 42 topmod
synth -top top
write_verilog synth.v
regression/issue_00132/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00133/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00134/issue_00134.ys 0 → 100644
read_verilog ../top.v
hierarchy -top task_bug
proc; opt; memory; dff2dffe; wreduce; clean; opt
write_verilog -noexpr -norename result.out
regression/issue_00134/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] a = 0;
wire [15:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.in_data (a ),
.do (y )
);
genvar index;
generate
for (index=0; index <= 15; index=index+1)
begin: gen_code_label
assert_X check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00134/top.v
module top ( in_data, do );
module task_bug ( in_data, do );
input [15:0] in_data;
output [15:0] do;
......
regression/issue_00160/issue_00160.ys 0 → 100644
read_verilog ../top.v
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
#equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_LUT4
select -assert-count 2 t:SB_DFFE
select -assert-none t:SB_LUT4 t:SB_DFFE %% t:* %D
regression/issue_00160/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg ce = 1;
wire d;
always @(posedge clk)
begin
a = a + 1;
end
top uut (
.CLKIN(clk),
.A (a ),
.CE (ce),
.D1 (d)
);
assert_X check_output(clk,d);
endmodule
regression/scripts/issue_00171.ys → regression/issue_00171/issue_00171.ys
......@@ -3,5 +3,3 @@ proc; opt; fsm; opt; memory; opt; techmap; opt
scc -all_cell_types
#and then put each found SCC into a module using submod.
scc -all_cell_types
synth -top top
write_verilog synth.v
regression/issue_00171/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 1;
reg ce = 1;
wire [3:0] count;
reg [3:0] count_p;
always @(posedge clk)
begin
rst = 0;
end
always @(posedge clk)
if (rst)
count_p <= 4'd0;
else if (ce)
count_p <= count_p + 4'd1;
top uut (
.clk(clk),
.rst (rst ),
.en (ce),
.count (count)
);
genvar index;
generate
for (index=0; index <= 3; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,count[index],count_p[index]);
end
endgenerate
endmodule
regression/issue_00173/issue_00173.ys 0 → 100644
read_verilog ../top.v
proc
regression/issue_00173/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [2:0] o;
reg [2:0] i;
always @(posedge clk)
i <= i + 1;
top uut (i[0],i[1],i[2],o[0],o[1],o[2]);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],i[index]);
end
endgenerate
endmodule
regression/issue_00174/abc.rc deleted 100644 → 0
# global parameters
set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
set backup # saves backup networks retrived by "undo" and "recall"
set savesteps 1 # sets the maximum number of backup networks to save
set progressbar # display the progress bar
# program names for internal calls
set dotwin dot.exe
set dotunix dot
set gsviewwin gsview32.exe
set gsviewunix gv
set siswin sis.exe
set sisunix sis
set mvsiswin mvsis.exe
set mvsisunix mvsis
set capowin MetaPl-Capo10.1-Win32.exe
set capounix MetaPl-Capo10.1
set gnuplotwin wgnuplot.exe
set gnuplotunix gnuplot
# standard aliases
alias b balance
alias cl cleanup
alias clp collapse
alias esd ext_seq_dcs
alias f fraig
alias fs fraig_sweep
alias fsto fraig_store
alias fres fraig_restore
alias ft fraig_trust
alias lp lutpack
alias pd print_dsd
alias pex print_exdc -d
alias pf print_factor
alias pfan print_fanio
alias pl print_level
alias pio print_io
alias pk print_kmap
alias ps print_stats
alias psu print_supp
alias psy print_symm
alias pun print_unate
alias q quit
alias r read
alias r3 retime -M 3
alias r3f retime -M 3 -f
alias r3b retime -M 3 -b
alias ren renode
alias rh read_hie
alias rl read_blif
alias rb read_bench
alias ret retime
alias rp read_pla
alias rt read_truth
alias rv read_verilog
alias rvl read_verlib
alias rsup read_super mcnc5_old.super
alias rlib read_library
alias rlibc read_library cadence.genlib
alias rw rewrite
alias rwz rewrite -z
alias rf refactor
alias rfz refactor -z
alias re restructure
alias rez restructure -z
alias rs resub
alias rsz resub -z
alias sa set autoexec ps
alias scl scleanup
alias sif if -s
alias so source -x
alias st strash
alias sw sweep
alias ssw ssweep
alias tr0 trace_start
alias tr1 trace_check
alias trt "r c.blif; st; tr0; b; tr1"
alias u undo
alias w write
alias wa write_aiger
alias wb write_bench
alias wc write_cnf
alias wh write_hie
alias wl write_blif
alias wp write_pla
alias wv write_verilog
# standard scripts
alias share "b; ren -s; fx; b"
alias sharedsd "b; ren -b; dsd -g; sw; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias resyn2a "b; rw; b; rw; rwz; b; rwz; b"
alias resyn3 "b; rs; rs -K 6; b; rsz; rsz -K 6; b; rsz -K 5; b"
alias compress "b -l; rw -l; rwz -l; b -l; rwz -l; b -l"
alias compress2 "b -l; rw -l; rf -l; b -l; rw -l; rwz -l; b -l; rfz -l; rwz -l; b -l"
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
alias rwsat "st; rw -l; b -l; rw -l; rf -l"
alias rwsat2 "st; rw -l; b -l; rw -l; rf -l; fraig; rw -l; b -l; rw -l; rf -l"
alias shake "st; ps; sat -C 5000; rw -l; ps; sat -C 5000; b -l; rf -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000; rwz -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000"
# resubstitution scripts for the IWLS paper
alias src_rw "st; rw -l; rwz -l; rwz -l"
alias src_rs "st; rs -K 6 -N 2 -l; rs -K 9 -N 2 -l; rs -K 12 -N 2 -l"
alias src_rws "st; rw -l; rs -K 6 -N 2 -l; rwz -l; rs -K 9 -N 2 -l; rwz -l; rs -K 12 -N 2 -l"
alias resyn2rs "b; rs -K 6; rw; rs -K 6 -N 2; rf; rs -K 8; b; rs -K 8 -N 2; rw; rs -K 10; rwz; rs -K 10 -N 2; b; rs -K 12; rfz; rs -K 12 -N 2; rwz; b"
alias compress2rs "b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; rs -K 8 -N 2 -l; rw -l; rs -K 10 -l; rwz -l; rs -K 10 -N 2 -l; b -l; rs -K 12 -l; rfz -l; rs -K 12 -N 2 -l; rwz -l; b -l"
# experimental implementation of don't-cares
alias resyn2rsdc "b; rs -K 6 -F 2; rw; rs -K 6 -N 2 -F 2; rf; rs -K 8 -F 2; b; rs -K 8 -N 2 -F 2; rw; rs -K 10 -F 2; rwz; rs -K 10 -N 2 -F 2; b; rs -K 12 -F 2; rfz; rs -K 12 -N 2 -F 2; rwz; b"
alias compress2rsdc "b -l; rs -K 6 -F 2 -l; rw -l; rs -K 6 -N 2 -F 2 -l; rf -l; rs -K 8 -F 2 -l; b -l; rs -K 8 -N 2 -F 2 -l; rw -l; rs -K 10 -F 2 -l; rwz -l; rs -K 10 -N 2 -F 2 -l; b -l; rs -K 12 -F 2 -l; rfz -l; rs -K 12 -N 2 -F 2 -l; rwz -l; b -l"
# minimizing for FF literals
alias fflitmin "compress2rs; ren; sop; ps -f"
# temporaries
#alias t "rvl th/lib.v; rvv th/t2.v"
#alias t "so c/pure_sat/test.c"
#alias t "r c/14/csat_998.bench; st; ps"
#alias t0 "r res.blif; aig; mfs"
#alias t "r res2.blif; aig; mfs"
#alias tt "r a/quip_opt/nut_001_opt.blif"
#alias ttb "wh a/quip_opt/nut_001_opt.blif 1.blif"
#alias ttv "wh a/quip_opt/nut_001_opt.blif 1.v"
alias reach "st; ps; compress2; ps; qrel; ps; compress2; ps; qreach -v; ps"
alias qs1 "qvar -I 96 -u; ps; qbf -P 96"
alias qs2 "qvar -I 96 -u; qvar -I 97 -u; ps; qbf -P 96"
alias qs3 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; ps; qbf -P 96"
alias qs4 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; ps; qbf -P 96"
alias qs5 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; ps; qbf -P 96"
alias qs6 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; ps; qbf -P 96"
alias qs7 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; ps; qbf -P 96"
alias qs8 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; ps; qbf -P 96"
alias qs9 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; ps; qbf -P 96"
alias qsA "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; qvar -I 105 -u; ps; qbf -P 96"
alias chnew "st; haig_start; resyn2; haig_use"
alias chnewrs "st; haig_start; resyn2rs; haig_use"
alias stdsd "r test/6in.blif; st; ps; u; bdd; dsd -g; st; ps"
alias trec "rec_start; r c.blif; st; rec_add; rec_use"
alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use"
alias trec5 "rec_start -K 5; r i10.blif; st; rec_add; rec_use"
alias trec6 "rec_start -K 6; r i10.blif; st; rec_add; rec_use"
alias trec7 "rec_start -K 7; r i10.blif; st; rec_add; rec_use"
alias trec8 "rec_start -K 8; r i10.blif; st; rec_add; rec_use"
alias trec10 "rec_start -K 10; r i10.blif; st; rec_add; rec_use"
alias trec12 "rec_start -K 12; r i10.blif; st; rec_add; rec_use"
#alias tsh "r i10_if.blif; st; ps; u; sw; st; ps; cec"
alias tst4 "r i10_if4.blif; st; ps; r x/rec4_.blif; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst4n "r i10_if4.blif; st; ps; r 5npn/all_functions.aig; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst6 "r i10_if6.blif; st; ps; r x/rec6_16_.blif; st; rec_start; r i10_if6.blif; st -r; ps; cec"
#alias t "r c.blif; st; wc c.cnf"
#alias t "r test/dsdmap6.blif; lutpack -vw; cec"
#alias t "r i10_if4.blif; lp"
#alias t1 "r pj1_if4.blif; lp"
#alias t2 "r pj1_if6.blif; lp"
#alias t "r pj/pj1.blif; st; dfraig -v"
#alias t "r c/16/csat_2.bench; st; dfraig -C 100 -v -r"
#alias t "r c/16/csat_147.bench; st; dfraig -C 10 -v -r"
#alias t "r i10.blif; st; ps; csweep; ps; cec"
#alias t "r c/5/csat_777.bench; st; csweep -v"
#alias t "r i10.blif; st; drw -v"
alias t "r c.blif; st; drf"
regression/issue_00174/abc.tcl deleted 100644 → 0
source abc.rc;
print_lut;
resyn;
regression/scripts/issue_00174.ys → regression/issue_00174/issue_00174.ys
......@@ -5,5 +5,3 @@ proc
opt -full
techmap
abc -lut 6
synth -top top
write_verilog synth.v
regression/issue_00174/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [5:0] o;
reg [5:0] i;
wire [5:0] wave_out;
always @(posedge clk)
i <= i + 1;
wire [31:0] w = 1-i;
assign wave_out = w/2;
top uut (i,o);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],wave_out[index]);
end
endgenerate
endmodule
regression/scripts/issue_00175.ys → regression/issue_00175/issue_00175.ys
......@@ -9,5 +9,3 @@ setundef -zero
opt -full -fine
setundef -zero
opt -full -fine
synth -top top
write_verilog synth.v
regression/issue_00175/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire GC;
wire GC_p;
reg E = 0;
always @(posedge clk)
E = ~E;
reg ED;
always@(*) begin
if(~clk)
ED = E;
end
assign GC_p = clk & ED;
top uut (clk,CG,E);
assert_dff check_output(clk,GC,GC_p);
endmodule
regression/scripts/issue_00182.ys → regression/issue_00182/issue_00182.ys
read_verilog ../top.v
synth_ice40 -blif litescope.bli -top top
write_verilog synth.v
regression/issue_00182/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
endmodule
regression/scripts/issue_00183.ys → regression/issue_00183/issue_00183.ys
read_verilog ../top.v
synth_ice40 -top top -blif test.blif
write_verilog synth.v
regression/issue_00183/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire out;
top uut (clk,out);
assert_dff check_output (clk,out,1'b1);
endmodule
regression/issue_00186/issue_00186.pat 0 → 100644
assign _07_\[0\] = adr\[0\] ? \\ram\[3\] \[0\] : \\ram\[2\] \[0\];
assign _07_\[1\] = adr\[0\] ? \\ram\[3\] \[1\] : \\ram\[2\] \[1\];
regression/scripts/issue_00186.ys → regression/issue_00186/issue_00186.ys
read_verilog -DTEST_1 ../top.v
hierarchy -top top
proc
memory
proc; memory
opt -full
techmap
write_verilog -noattr synth.v
write_verilog -noattr result.out
regression/issue_00186/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] adr = 0;
reg [1:0] din = 0;
wire [1:0] q;
reg mem_init = 0;
always @(posedge clk) begin
#3;
din <= din + 1;
adr <= adr + 1;
end
always @(posedge adr) begin
#10;
if(adr == 2'b11)
mem_init <= 1;
end
top uut (adr,clk,din,q);
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .A(q));
endmodule
module uut_mem_checker(input clk, input init, input [1:0] A);
always @(posedge clk)
begin
#1;
if (init == 1 & A === 2'bXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00194/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire out;
top uut (clk,out);
assert_dff check_output (clk,out,1'b1);
endmodule
regression/issue_00196/issue_00196_fail.pat 0 → 100644
ERROR: Found posedge/negedge event on a signal that is not 1 bit wide!
regression/scripts/issue_00196.ys → regression/issue_00196/issue_00196_fail.ys
read_verilog ../top.v
synth_greenpak4 -json 3pdrive.json
write_verilog synth.v
regression/issue_00196/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire a,b,c,d,e,f;
top uut(clk,a,b,c,d,e,f);
endmodule
regression/issue_00210/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [9:0] a;
top uut(a);
endmodule
regression/issue_00253/issue_00253.pat 0 → 100644
State encoding:
0: 3'100
1: 3'010
2: 3'001
3: 3'101
4: 3'011
regression/issue_00253/issue_00253.ys 0 → 100644
read_verilog ../top.v
proc; opt
tee -o result.out fsm -encoding binary
techmap; opt
regression/issue_00253/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] in = 2;
reg [1:0] count = 0;
reg init = 0;
wire [7:0] out;
always @(posedge clk)
begin
in = in + 7;
count = count + 1;
if (count == 2'b11)
init = 1;
end
top uut(clk,in,out);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
check_X check_output(clk,init,out[index]);
end
endgenerate
endmodule
module check_X(input clk,input init, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX && init == 1'b1)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/scripts/issue_00114.ys → regression/issue_00282/issue_00282.ys
read_verilog ../top.v
synth -top top
write_verilog synth.v
#synth_ice40 -top top
select -assert-count 1 t:$_DFF_P_
regression/issue_00282/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] in = 2;
reg [1:0] count = 0;
reg init = 0;
wire [7:0] out;
always @(posedge clk)
begin
in = in + 7;
count = count + 1;
if (count == 2'b11)
init = 1;
end
top uut(clk,in,out);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
check_X check_output(clk,init,out[index]);
end
endgenerate
endmodule
module check_X(input clk,input init, input A);
always @(posedge clk)
begin
#1;
if (A === 1'bX && init == 1'b1)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00282/top.v
module top(input clk,input[3:0] in, output [7:0] out);
reg[2:0] state;
always @(posedge clk) begin
out<=0;
case (state)
0: begin
if(in == 0) begin
state<=1;
out<=0;
end
if(in == 1) begin
state<=2;
out<=1;
end
if(in == 2) begin
state<=5;
out<=2;
end
end
1: begin
if(in == 0) begin
state<=1;
out<=3;
end
if(in == 1) begin
state<=3;
out<=4;
end
if(in == 2) begin
state<=1;
out<=5;
end
if(in == 3) begin
state<=3;
out<=6;
end
if(in == 4) begin
state<=2;
out<=7;
end
if(in == 5) begin
state<=5;
out<=8;
end
if(in == 6) begin
state<=3;
out<=9;
end
if(in == 7) begin
state<=5;
out<=10;
end
if(in == 8) begin
state<=3;
out<=11;
end
if(in == 9) begin
state<=2;
out<=12;
end
end
2: begin
if(in == 0) begin
state<=2;
out<=13;
end
if(in == 1) begin
state<=2;
out<=14;
end
if(in == 2) begin
state<=1;
out<=15;
end
if(in == 3) begin
state<=1;
out<=16;
end
if(in == 4) begin
state<=2;
out<=17;
end
if(in == 5) begin
state<=2;
out<=18;
end
if(in == 6) begin
state<=2;
out<=19;
end
if(in == 7) begin
state<=5;
out<=20;
end
if(in == 8) begin
state<=5;
out<=21;
end
if(in == 9) begin
state<=2;
out<=22;
end
end
3: begin
if(in == 0) begin
state<=3;
out<=23;
end
if(in == 1) begin
state<=3;
out<=24;
end
if(in == 2) begin
state<=3;
out<=25;
end
if(in == 3) begin
state<=3;
out<=26;
end
if(in == 4) begin
state<=4;
out<=27;
end
if(in == 5) begin
state<=5;
out<=28;
end
if(in == 6) begin
state<=3;
out<=29;
end
if(in == 7) begin
state<=5;
out<=30;
end
if(in == 8) begin
state<=3;
out<=31;
end
if(in == 9) begin
state<=2;
out<=32;
end
end
4: begin
if(in == 0) begin
state<=4;
out<=33;
end
if(in == 1) begin
state<=4;
out<=34;
end
if(in == 2) begin
state<=3;
out<=35;
end
if(in == 3) begin
state<=3;
out<=36;
end
if(in == 4) begin
state<=4;
out<=37;
end
if(in == 5) begin
state<=2;
out<=38;
end
if(in == 6) begin
state<=2;
out<=39;
end
if(in == 7) begin
state<=5;
out<=40;
end
if(in == 8) begin
state<=5;
out<=41;
end
if(in == 9) begin
state<=2;
out<=42;
end
end
5: begin
if(in == 0) begin
state<=1;
out<=43;
end
if(in == 1) begin
state<=1;
out<=44;
end
if(in == 2) begin
state<=1;
out<=45;
end
if(in == 3) begin
state<=1;
out<=46;
end
if(in == 4) begin
state<=2;
out<=47;
end
if(in == 5) begin
state<=5;
out<=48;
end
if(in == 6) begin
state<=5;
out<=49;
end
if(in == 7) begin
state<=5;
out<=50;
end
if(in == 8) begin
state<=5;
out<=51;
end
if(in == 9) begin
state<=2;
out<=52;
end
end
endcase
end
module top(input clk,input in, output out);
always @(posedge clk)
out<=in;
endmodule
regression/issue_00283/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire y;
top uut(clk,1'b1,y);
assert_X check_output(clk,y);
endmodule
regression/issue_00283/top.v
module top(input clk, enable, output reg y);
module top
#(parameter WIDTH = 64, C_WIDTH = 8, DE = 4)
(
input clk,
input reset,
input [C_WIDTH*WIDTH-1:0] c_data_in_port,
input [DE*C_WIDTH -1:0] d_one_hot,
input [C_WIDTH -1:0] c_data_in_en,
wire [1:0] foo [1:0];
integer i;
initial begin
for (i=0;i<=1;i=i+1)
foo[i] = 2'b11;
output reg [DE*WIDTH-1:0] d_data_out_port,
output reg [DE-1:0] d_data_out_en
);
reg [ WIDTH-1:0] clients_data_in [ C_WIDTH-1:0];
reg [ C_WIDTH-1:0] devices_one_hot_client_sel [ DE-1:0];
reg [ WIDTH-1:0] devices_data_out [ DE-1:0];
reg [ WIDTH-1:0] clients_data_in_s [ C_WIDTH-1:0];
reg [ C_WIDTH-1:0] devices_one_hot_client_sel_s [ DE-1:0];
wire [ WIDTH-1:0] devices_data_out_p [ DE-1:0];
wire [ C_WIDTH-1:0] clients_data_rotate [ WIDTH-1:0];
wire [ DE-1:0] devices_data_rotate [ WIDTH-1:0];
reg [ DE-1:0] clients_one_hot_device_sel [ C_WIDTH-1:0];
wire [ DE-1:0] dev_en;
wire [ DE-1:0] data_out_en;
integer client, device;
always @*
begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
clients_data_in[client] = c_data_in_port[client*WIDTH+:WIDTH];
end
end
always @*
begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
clients_one_hot_device_sel[client] = d_one_hot[client*DE+:DE];
end
end
always @(posedge clk)
if (enable)
for (i = 0; i < 2; i=i+1)
y <= foo[0][0];
always @*
begin
for (device = 0; device < DE; device = device + 1) begin
for(client = 0; client < C_WIDTH; client = client + 1) begin
devices_one_hot_client_sel[device][client] = clients_one_hot_device_sel[client][device];
end
end
end
genvar k;
integer rowsel;
genvar i, j, nw;
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][WIDTH-1:1] <= 'b0;
else begin
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
if (dev_en[rowsel]==1'b1)
devices_data_out[rowsel][WIDTH-1:1] <= devices_data_out_p[rowsel][WIDTH-1:1];
end
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][0] <= 1'b0;
else
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
devices_data_out[rowsel][0] <= devices_data_out_p[rowsel][0];
always @*
begin
for(rowsel = 0; rowsel < C_WIDTH; rowsel=rowsel+1) begin
clients_data_in_s[rowsel][WIDTH-1:0] = clients_data_in[rowsel];
end
end
always @*
begin
for(rowsel = 0; rowsel < DE; rowsel=rowsel+1) begin
devices_one_hot_client_sel_s[rowsel][C_WIDTH-1:0] = devices_one_hot_client_sel[rowsel][C_WIDTH-1:0];
end
end
generate
for (i = 0; i < DE; i=i+1) begin:gen_i3
assign dev_en[i] = |devices_one_hot_client_sel_s[i][C_WIDTH-1:0];
end
endgenerate
generate
for (i = 0; i < DE; i=i+1) begin:gen_i4
assign data_out_en[i] = |devices_one_hot_client_sel[i][C_WIDTH-1:0];
end
endgenerate
always @(posedge clk or negedge reset)
if (!reset)
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
d_data_out_en[rowsel] <= 1'b0;
else
for (rowsel = 0; rowsel < DE; rowsel=rowsel+1)
d_data_out_en[rowsel] <= data_out_en[rowsel];
generate
for (i = 0; i < C_WIDTH; i=i+1) begin:gen_i
for (j = 0; j < WIDTH; j=j+1) begin:gen_j
assign clients_data_rotate[j][i] = clients_data_in_s[i][j];
end
end
endgenerate
generate
for (nw = 0; nw < WIDTH; nw=nw+1) begin : gen_nw
for (i = 0; i < DE; i=i+1) begin:gen_label
assign devices_data_rotate[nw][i] = |(clients_data_rotate[nw] & devices_one_hot_client_sel_s[i]);
end
end
endgenerate
generate
for (i = 0; i < WIDTH; i=i+1) begin:gen_i2
for (j = 0; j < DE; j=j+1) begin:gen_j2
assign devices_data_out_p[j][i] = devices_data_rotate[i][j];
end
end
endgenerate
always @*
begin
for (device = 0; device < DE; device = device + 1) begin
d_data_out_port[device*WIDTH+:WIDTH] = devices_data_out[device];
end
end
endmodule
regression/issue_00287/issue_00287.ys 0 → 100644
tee -o result.out read_verilog -sv ../top.v
regression/issue_00287/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [6:0] D = 0;
reg [1:0] S = 0;
wire [1:0] Y;
reg [1:0] Y_p;
always @(posedge clk)
begin
D = D + 3;
S = S + 1;
end
always @* begin : block
reg [3:0] data [0:3];
data[0] = D[3:0];
data[1] = D[4:1];
data[2] = D[5:2];
data[3] = D[6:3];
Y_p = data[S];
end
top uut(D,S,Y);
assert_dff check_Y0 (clk,Y[0],Y_p[0]);
assert_dff check_Y1 (clk,Y[1],Y_p[1]);
endmodule
regression/issue_00289/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire o;
top uut(clk,o);
assert_dff check_o (clk,clk,o);
endmodule
regression/issue_00291/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 0;
reg any_pop = 0;
reg any_push = 0;
always @(posedge clk)
begin
rst = 1;
#1
any_pop = ~any_pop;
#3
any_push = ~any_push;
end
top uut(rst,clk,any_push,any_pop);
endmodule
regression/scripts/issue_00300.ys → regression/issue_00300/issue_00300.ys
......@@ -7,11 +7,9 @@ dump
write_ilang foo.ilang
memory_collect
stat
dump t:$mem
#dump t:$mem
design -reset
read_ilang foo.ilang
stat
memory_collect
dump t:$mem
write_verilog synth.v
tee -o result.out dump t:$mem
regression/issue_00300/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] addr = 0;
reg [7:0] wdata = 0;
wire [7:0] rdata;
wire [7:0] rdata_o;
always @(posedge clk)
begin
addr = addr + 1;
wdata = wdata + 17;
end
reg [7:0] memory [255:0];
assign rdata = memory[addr];
always @(posedge clk) memory[addr] <= wdata;
top uut(clk,addr,wdata,rdata_o);
uut_mem_checker port_b_test(.clk(clk), .A(rdata), .B(rdata_o));
endmodule
module uut_mem_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A == B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/scripts/issue_00306.ys → regression/issue_00306/issue_00306.ys
......@@ -2,6 +2,3 @@ read_verilog ../top.v
proc
opt -full
synth -top top
write_verilog synth.v
regression/issue_00306/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] a = 0;
wire res_p;
wire res;
always @(posedge clk)
begin
a = a + 1;
end
assign res_p = a < 6'b100000;
top uut(a,res);
assert_dff check_res (clk,res, res_p);
endmodule
regression/issue_00314/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
reg [7:0] b = 0;
wire [7:0] z;
always @(posedge clk)
begin
a = a + 1;
b = b + 7;
end
top uut(a,b,z);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,z[index]);
end
endgenerate
endmodule
regression/issue_00317/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/scripts/issue_00329.ys → regression/issue_00329/issue_00329.ys
read_verilog -mem2reg ../top.v
write_verilog result.log
write_verilog result.out
regression/scripts/issue_00341.ys → regression/issue_00341/issue_00341.ys
......@@ -4,7 +4,3 @@ equiv_make gold top_w equiv
opt -purge
equiv_simple
equiv_status -assert
design -reset
read_verilog ../top.v
synth
write_verilog synth.v
regression/issue_00341/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i1,i2 = 0;
wire o1g,o2g;
wire o1r,o2r;
wire o1w,o2w;
wire o1gt,o2gt;
wire o1rt,o2rt;
wire o1wt,o2wt;
always @(posedge clk) begin
i1 <= i1 + 1;
i2 <= i2 + 1;
end
gold uut_g (
i1,i2,o1g,o2g
);
top_r uut_r (
i1,i2,o1r,o2r
);
top_w uut_w (
i1,i2,o1w,o2w
);
goldt uut_gt (
i1,i2,o1gt,o2gt
);
top_rt uut_rt (
i1,i2,o1rt,o2rt
);
top_wt uut_wt (
i1,i2,o1wt,o2wt
);
assert_dff gold_test(clk,o1g,o1gt);
assert_dff top_r_test(clk,o1r,o1rt);
assert_dff top_w_test(clk,o1w,o1wt);
endmodule
module goldt(input i1, input i2, output o2, output o1);
wire _1_;
assign o2 = i1 & i2;
assign _1_ = i1 | i2;
assign o1 = _1_ & o2;
endmodule
module top_rt( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 && i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
module top_wt( i1, i2, o1, o2 );
input i1, i2;
output o1, o2;
wire w4;
assign o2 = (i2 & i1);
assign w4 = ((i2 & i1) | (i2) | (i1));
assign o1 = ((w4 & o2));
endmodule
regression/issue_00342/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] addr = 0;
reg [7:0] wdata = 0;
wire [7:0] rdata;
wire [7:0] rdata_o;
always @(posedge clk)
begin
addr = addr + 1;
wdata = wdata + 17;
end
logic [8-1:0] mem [8-1:0];
assign rdata_o = mem[addr];
always @*
if (clk)
mem[addr] <= wdata;
top uut(rdata,wdata,addr,clk,clk);
uut_mem_checker port_b_test(.clk(clk), .A(rdata), .B(rdata_o));
endmodule
module uut_mem_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00342/top.v
......@@ -11,3 +11,11 @@ module top #(parameter AWIDTH=8,
always_latch
if (!cs_n && !r_wn) mem[addr] <= wdata;
endmodule
module generic_decoder
#(num_code_bits = 3,
localparam num_out_bits = 1 << num_code_bits)
(input [num_code_bits-1:0] A,
output reg [num_out_bits-1:0] Y);
endmodule
regression/issue_00349/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
reg z_p;
wire z;
always @(posedge clk) begin
in <= in + 1;
end
always @*
z_p <= in[0] ~& in[1];
top uut (in[0],in[1],z);
assert_dff z_test(clk,z,z_p);
endmodule
regression/issue_00350/issue_00350.ys 0 → 100644
read_verilog -sv ../top.v
synth
abc -dff -g AND
opt
write_aiger -ascii -symbols <file.out>
design -reset
read_aiger <file.out>
write_verilog result.out
regression/issue_00350/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i;
wire o_p;
wire o;
always @(posedge clk) begin
#2
i <= ~i;
end
reg q = 0;
always @(posedge clk) q <= 1;
assign o_p = q & i;
top uut (clk,i,o);
assert_dff z_test(clk,o,o_p);
endmodule
regression/issue_00350/top.v
module top (input clk, input i, output o);
reg q = 0;
always @(posedge clk) q <= 1;
assign o = q & i;
module test
( input clk
, input in
, output out
);
reg [1:0] state = 0;
always @(posedge clk)
case (state)
0:
if (!in || in)
state <= 1;
else
state <= state;
1:
if (in)
state <= 1;
else
if (!in)
state <= 1;
else
state <= state;
endcase
always @(*)
case (state)
0:
out = 0;
1:
begin
if (in)
out = 1;
if (!in)
out = 0;
end
endcase
endmodule
regression/scripts/issue_00361.ys → regression/issue_00361/issue_00361.ys
read_verilog -sv ../top.v
prep
alumacc
maccmap -unmap
synth -top top
write_verilog synth.v
select -assert-count 63 t:$add
select -assert-count 2 t:$macc
select -assert-count 65 t:$mul
regression/issue_00361/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] A, B, C, D = 0;
reg [127:0] E, F = 0;
reg [127:0] X_p, Y_p;
wire [127:0] X,Y;
always @(posedge clk)
begin
A = A + 248;
B = B + 338;
C = C + 435;
D = D + 282;
E = E + 1248;
F = F + 2148;
end
integer i;
always @* begin
X_p = A*B + E;
Y_p = F;
for (i = 0; i < 64; i=i+1)
Y_p = Y_p + C[i]*D[i];
end
top uut (A,B,C,D,E,F,X,Y);
uut_checker X_test(.clk(clk), .A(X), .B(X_p));
uut_checker Y_test(.clk(clk), .A(Y), .B(Y_p));
endmodule
module uut_checker(input clk, input [127:0] A, input [127:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00362/issue_00362_fail.pat 0 → 100644
ERROR: Output port top.inst.b (inst) is connected to constants: 1'1
regression/issue_00362/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [63:0] A, B, C, D = 0;
reg [127:0] E, F = 0;
reg [127:0] X_p, Y_p;
wire [127:0] X,Y;
always @(posedge clk)
begin
A = A + 248;
B = B + 338;
C = C + 435;
D = D + 282;
E = E + 1248;
F = F + 2148;
end
integer i;
always @* begin
X_p = A*B + E;
Y_p = F;
for (i = 0; i < 64; i=i+1)
Y_p = Y_p + C[i]*D[i];
end
top uut (A,B,C,D,E,F,X,Y);
uut_checker X_test(.clk(clk), .A(X), .B(X_p));
uut_checker Y_test(.clk(clk), .A(Y), .B(Y_p));
endmodule
module uut_checker(input clk, input [127:0] A, input [127:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/scripts/issue_00291.ys → regression/issue_00372/issue_00372.ys
read_verilog -sv ../top.v
synth -top top
write_verilog synth.v
select -assert-count 1 t:$_DFF_P_
regression/issue_00372/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg d = 0;
wire q;
reg q_p = 0;
always @(posedge clk)
q_p <= d;
top uut (clk,d,q);
assert_dff q_test(clk,q,q_p);
endmodule
regression/scripts/issue_00391.ys → regression/issue_00391/issue_00391.ys
read_verilog -sv ../top.v
prep -top top -nordff
write_smt2 top.smt2
design -reset
read_verilog -sv ../top_clean.v
synth -top top
write_verilog synth.v
regression/issue_00391/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (clk);
endmodule
regression/issue_00391/top_clean.v deleted 100644 → 0
module decode1_1(input clk,
input rst,
input [31:0] in_count,
input in_valid,
output in_ready,
input out_ready,
output out_valid);
reg [31:0] r_remaining_count;
reg r_valid;
reg r_ready;
assign out_valid = r_valid;
assign in_ready = r_ready;
always @(posedge clk) begin
if (rst) begin
r_remaining_count <= 0;
r_valid <= 0;
r_ready <= 0;
end else begin
if (r_remaining_count == 0) begin
if (r_ready && in_valid) begin
r_remaining_count <= in_count;
r_valid <= in_count != 0;
r_ready <= 0;
end else begin
r_ready <= 1;
r_valid <= 0;
end
end else begin
r_valid <= !(r_remaining_count == 1 && out_ready && out_valid);
r_ready <= 0;
if (out_valid && out_ready) begin
r_remaining_count <= r_remaining_count - 1;
end
end
end
end
endmodule // decode1_1
module top(input clk);
wire out_valid;
wire [31:0] out_data;
wire out_ready = 1'b1;
reg [31:0] cycles;
wire rst = (cycles < 3);
wire in_ready;
reg [31:0] test_counts [0:1];
reg [31:0] test_index;
wire in_valid = (test_index < 1) && (cycles > 2);
reg [9:0] out_data_index;
always @(posedge clk)
begin
cycles <= cycles + 1;
end
always @(posedge clk)
begin
if (cycles < 1) begin
//test_counts[cycles] <= $anyseq;
end
end
initial begin
cycles = 0;
test_index = 0;
end
decode1_1 decoder(clk, rst,
test_counts[test_index],
in_valid,
in_ready,
out_ready,
out_valid);
always @(posedge clk) begin
if (!rst) begin
// assert(out_data_index <= 0);
if (in_valid && in_ready) begin
test_index <= test_index + 1;
end
if (out_ready && out_valid) begin
out_data_index <= out_data_index + 1;
end
end
end // always @ (posedge clk)
endmodule
regression/issue_00432/issue_00432.ys 0 → 100644
read_verilog -sv ../top.v
write_verilog result.v
design -reset
read_verilog result.v
hierarchy -check
regression/issue_00432/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a;
reg [7:0] b;
wire [7:0] c_p;
wire [7:0] c;
always @(posedge clk)
begin
a = a + 3;
b = b + 7;
end
assign c_p = a[$signed(b) +: 8];
top uut (a, b, c);
uut_checker c_test(.clk(clk), .A(c_p), .B(c));
endmodule
module uut_checker(input clk, input [7:0] A, input [7:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/issue_00444/issue_00444.ys 0 → 100644
read_verilog -formal ../top.v
prep -top top
regression/issue_00444/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] a;
wire [31:0] c;
always @(posedge clk)
begin
a = a + 3;
end
top uut (clk, a, c);
uut_checker c_test(.clk(clk), .A(c), .B(c));
endmodule
module uut_checker(input clk, input [31:0] A, input [31:0] B);
always @(posedge clk)
begin
#1;
if (A != B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," != ",B);
$stop;
end
end
endmodule
regression/scripts/issue_00449.ys → regression/issue_00449/issue_00449.ys
read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00457.ys → regression/issue_00457/issue_00457.ys
read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
regression/issue_00457/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00474/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00474/top.v deleted 100644 → 0
module top(i_clk,b);
input i_clk;
output b;
reg f_past_gbl_clock_valid;
initial f_past_gbl_clock_valid = 0;
always @(posedge i_clk)
f_past_gbl_clock_valid <= 1'b1;
assign b = f_past_gbl_clock_valid;
endmodule
regression/issue_00481/issue_00481.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -blif tlt.blif
regression/issue_00481/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire b;
top uut (clk,b);
assert_X b_test(.clk(clk), .A(b));
endmodule
regression/issue_00527/syn.tcl deleted 100644 → 0
# Basic synthesis file to replicate DFFSR bug
yosys -import
set libfile osu018_stdcells_edit.lib
read_verilog -sv sd_rrmux.v
# Vanilla synth flow
hierarchy
procs
fsm
opt
techmap
opt
dfflibmap -liberty $libfile
abc -liberty $libfile
clean
write_verilog sd_rrmux_osu.gv
regression/issue_00527/testcase deleted 100644 → 0
#!/bin/bash
yosys -t syn.tcl
if grep -q DFFSR sd_rrmux_osu.gv; then
echo "FAILED -- DFFSR present in netlist"
else
echo "PASSED -- DFFSR not present"
fi
regression/scripts/issue_00567.ys → regression/issue_00567/issue_00567.ys
......@@ -2,5 +2,3 @@ read_verilog ../top.v
synth_ice40 -nocarry
opt_clean
write_blif -attr -cname -param lut.eblif
write_verilog synth.v
regression/issue_00567/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [3:0] i = 0;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (i,b);
assert_Z b_test(.clk(clk), .A(b));
endmodule
regression/issue_00582/issue_00582_fail.pat 0 → 100644
ERROR: Failed to detect width for identifier \\valid!
regression/scripts/issue_00582.ys → regression/issue_00582/issue_00582_fail.ys
read_verilog ../top.v
synth_ice40 -top main -blif stencil.blif
write_verilog synth.v
regression/issue_00582/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire [4:0] b;
always @(posedge clk)
begin
i = i + 1;
end
main uut (b,clk);
assert_Z b_test(.clk(clk), .A(b[0]));
endmodule
regression/scripts/issue_00589.ys → regression/issue_00589/issue_00589.ys
......@@ -12,7 +12,4 @@ share -aggressive -force
opt
fsm
opt -fast
write_ilang dump.ilang
synth -top main
write_verilog synth.v
select -assert-count 1 t:$memrd
regression/issue_00589/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire [4:0] b;
always @(posedge clk)
begin
i = i + 1;
end
main uut (b,clk);
assert_Z b_test(.clk(clk), .A(b[0]));
endmodule
regression/issue_00594/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire [4:0] b;
always @(posedge clk)
begin
i = i + 1;
end
main uut (b,clk);
assert_Z b_test(.clk(clk), .A(b[0]));
endmodule
regression/issue_00603/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire [4:0] b;
always @(posedge clk)
begin
i = i + 1;
end
main uut (b,clk);
assert_Z b_test(.clk(clk), .A(b[0]));
endmodule
regression/scripts/issue_00628.ys → regression/issue_00628/issue_00628.ys
......@@ -11,7 +11,6 @@ abc -script +strash
#retime
#strash
clean
write_blif
synth_ice40 -top top
write_verilog synth.v
#write_blif
select -assert-count 16 t:SB_LUT4
regression/issue_00628/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16,b17;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,b1,b2,b3,b4,b5,b6,b7,b8,b9,b10,b11,b12,b13,b14,b15,b16,b17);
assert_Z b1_test(.clk(clk), .A(b1));
assert_Z b17_test(.clk(clk), .A(b17));
endmodule
regression/scripts/issue_00630.ys → regression/issue_00630/issue_00630.ys
read_verilog ../top.v
hierarchy
synth_ice40 -blif demo.blif
write_verilog synth.v
tee -o result.out synth_ice40 -blif demo.blif
regression/issue_00630/issue_00630_n.pat 0 → 100644
Warning: wire '$func$\func$demo.v:8$2$\arg' is assigned in a block at demo.v:4.
regression/issue_00630/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,b);
assert_Z b1_test(.clk(clk), .A(b));
endmodule
regression/issue_00635/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [4:0] i = 0;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,b);
assert_Z b1_test(.clk(clk), .A(b));
endmodule
regression/issue_00639/issue_00639_fail.pat 0 → 100644
ERROR: Found 3 unproven \$equiv cells in 'equiv_status -assert'.
regression/issue_00642/issue_00642.ys 0 → 100644
read_verilog -formal ../top.v
regression/issue_00642/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/issue_00644/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/scripts/issue_00655.ys → regression/issue_00655/issue_00655.ys
......@@ -17,9 +17,9 @@ read_verilog -I../verilog/config ../verilog/submodule/rtl/lm32_debug.v
read_verilog -I../verilog/config ../verilog/submodule/rtl/lm32_itlb.v
read_verilog -I../verilog/config ../verilog/submodule/rtl/lm32_dtlb.v
read_verilog -I../verilog/config ../top.v
# hierarchy -top top
hierarchy -top top
# proc; memory; opt; fsm; opt
attrmap -tocase keep -imap keep="true" keep=1 \
-imap keep="false" keep=0 -remove keep=0
tee -o result.log synth_xilinx -top top -edif top.edif
write_verilog synth.v
synth_xilinx -top top
write_edif -attrprop result.out
regression/issue_00655/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
wire serial_tx;
reg serial_rx;
reg clk100;
reg cpu_reset;
wire eth_ref_clk;
wire user_led0;
wire user_led1;
wire user_led2;
wire user_led3;
reg user_sw0;
reg user_sw1;
reg user_sw2;
reg user_sw3;
reg user_btn0;
reg user_btn1;
reg user_btn2;
reg user_btn3;
wire spiflash_1x_cs_n;
wire spiflash_1x_mosi;
reg spiflash_1x_miso;
wire spiflash_1x_wp;
wire spiflash_1x_hold;
wire [13:0] ddram_a;
wire [2:0] ddram_ba;
wire ddram_ras_n;
wire ddram_cas_n;
wire ddram_we_n;
wire ddram_cs_n;
wire [1:0] ddram_dm;
wire [15:0] ddram_dq;
wire [1:0] ddram_dqs_p;
wire [1:0] ddram_dqs_n;
wire ddram_clk_p;
wire ddram_clk_n;
wire ddram_cke;
wire ddram_odt;
wire ddram_reset_n;
top uut (
serial_tx,
serial_rx,
clk,
cpu_reset,
eth_ref_clk,
user_led0,
user_led1,
user_led2,
user_led3,
user_sw0,
user_sw1,
user_sw2,
user_sw3,
user_btn0,
user_btn1,
user_btn2,
user_btn3,
spiflash_1x_cs_n,
spiflash_1x_mosi,
spiflash_1x_miso,
spiflash_1x_wp,
spiflash_1x_hold,
ddram_a,
ddram_ba,
ddram_ras_n,
ddram_cas_n,
ddram_we_n,
ddram_cs_n,
ddram_dm,
ddram_dq,
ddram_dqs_p,
ddram_dqs_n,
ddram_clk_p,
ddram_clk_n,
ddram_cke,
ddram_odt,
ddram_reset_n
);
endmodule
regression/issue_00655/top.edif deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00655/top_wo_attrprop.edif deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00675/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/issue_00689/issue_00689.ys 0 → 100644
tee -o result.log read_verilog -sv ../top.v
synth -top top
regression/issue_00689/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/issue_00699/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
wire b;
always @(posedge clk)
begin
i = i + 1;
end
top uut (clk,i,b);
always @(posedge clk)
out <= $past(i,9);
assert_dff b1_test(.clk(clk), .test(b), .pat(out));
endmodule
regression/issue_00705/issue_00705.pat 0 → 100644
.MASK({ _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_, _18_ }),
regression/issue_00705/issue_00705.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -top top -blif top.blif
design -reset
read_blif -wideports top.blif
write_verilog result.out
regression/issue_00705/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [7:0] dbr; // Data bus READ
reg [7:0] addr = 0; // Address bus - eight bits
always @(posedge clk)
begin
addr = addr + 1;
end
top uut (
dbr, // Data bus READ
addr, // Address bus - eight bits
clk // Clock
);
assert_Z b1_test(clk,dbr[7]);
endmodule
regression/issue_00708/issue_00708.ys 0 → 100644
tee -o result.out read_verilog ../top.v
regression/issue_00708/top.v
module top;
`define MAX(_a, _b) ((_a) > (_b) ? (_a) : (_b))
localparam integer X = `MAX($clog2(1 << 17) - 18, 0);
initial $display("%d", X);
initial $display("X = %d", X);
endmodule
regression/issue_00737/issue_00737.ys 0 → 100644
tee -o result.out read_verilog -dump_ast1 ../top.v
regression/issue_00763/issue_00763_fail.pat 0 → 100644
ERROR: Invalid nesting of always blocks and/or initializations.
regression/issue_00763/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
reg b,u = 0;
always @(posedge clk)
begin
b = b + 1;
u = ~u;
end
top uut (clk,b,u);
endmodule
regression/scripts/issue_00767.ys → regression/issue_00767/issue_00767.ys
read_verilog -sv ../top.v;
prep -top top;
flatten;;
write_btor top.btor
write_verilog synth.v
write_btor result.out
regression/issue_00767/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
reg b,u = 0;
always @(posedge clk)
begin
b = b + 1;
u = ~u;
end
top uut (clk,b,u,out);
endmodule
regression/scripts/issue_00774.ys → regression/issue_00774/issue_00774.ys
read_verilog ../yosys_rocket/AsyncResetReg.v ../yosys_rocket/EICG_wrapper.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.v ../yosys_rocket/freechips.rocketchip.system.LowRiscConfig.behav_srams.v ../yosys_rocket/plusarg_reader.v ../yosys_rocket/SimDTM.v
tee -o result.log synth_ecp5 -blif foo.blif
synth_ecp5 -blif foo.blif
regression/issue_00781/issue_00781.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -blif test.blif
regression/issue_00781/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg i = 0;
reg out;
reg b,u = 0;
always @(posedge clk)
begin
b = b + 1;
u = ~u;
end
top uut (clk,b,u);
endmodule
regression/issue_00785/issue_00785.ys 0 → 100644
read_verilog ../top.v
synth_ice40
regression/issue_00790/issue_00790.ys 0 → 100644
read -formal ../top.v
prep -top mcve
select -assert-count 5 t:$assert
regression/issue_00790/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [3:0] D;
reg [1:0] S = 0;
reg [3:0] control = 0;
always @(posedge clk)
case(S)
2'b00: begin end
2'b01: control <= 4'h2;
2'b10: control <= 4'h4;
2'b11: control <= 4'h8;
default: control <= 4'h0;
endcase
top uut (
.clk (clk ),
.I (S ),
.O (D )
);
always @(posedge clk) begin
//#3;
S <= S + 1;
end
check_output out_test( .A(control), .B(D));
endmodule
module check_output(input [3:0] A, input [3:0] B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
regression/issue_00790/top.v
......@@ -7,16 +7,21 @@ module mcve(i_clk, i_value, o_value);
always @(posedge i_clk)
case(i_value)
2'b00: begin end
`ifndef BUG
2'b01: o_value <= 4'h2;
`else
2'b01: o_value <= 4'h3;
`endif
2'b10: o_value <= 4'h4;
2'b11: o_value <= 4'h8;
default: o_value <= 4'h1;
endcase
always @(*)
case(o_value)
4'h0: begin end
4'h1: assert(o_value == 4'h1);
4'h2: assert(o_value == 4'h2);
4'h4: assert(o_value == 4'h4);
4'h8: assert(o_value == 4'h8);
default: assert(0);
endcase
endmodule
module top (
......
regression/issue_00790/top_assert.v deleted 100644 → 0
module mcve(i_clk, i_value, o_value);
input wire i_clk;
input wire [1:0] i_value;
output reg [3:0] o_value;
initial o_value = 0;
always @(posedge i_clk)
case(i_value)
2'b00: begin end
`ifndef BUG
2'b01: o_value <= 4'h2;
`else
2'b01: o_value <= 4'h3;
`endif
2'b10: o_value <= 4'h4;
2'b11: o_value <= 4'h8;
default: o_value <= 4'h1;
endcase
always @(*)
case(o_value)
4'h0: begin end
4'h1: assert(o_value == 4'h1);
`ifndef BUG
4'h2: assert(o_value == 4'h2);
`else
4'h2: assert(o_value == 4'h3);
`endif
4'h4: assert(o_value == 4'h4);
4'h8: assert(o_value == 4'h8);
default: assert(0);
endcase
endmodule
module top (
input clk,
input [1:0] I,
output [3:0] O
);
mcve u_mcve (
.i_clk(clk),
.i_value(I),
.o_value(O)
);
endmodule
regression/issue_00807/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] x = 0;
wire y;
always @(posedge clk)
begin
x = x + 1;
end
top uut (x,y);
assert_X out_test (clk,y);
endmodule
regression/scripts/issue_00809.ys → regression/issue_00809/issue_00809.ys
read_verilog ../top.v
hierarchy -check -top top
proc; opt; memory; opt; fsm; opt; techmap; opt
abc
opt_clean
write_verilog synth.v
write_verilog result.out
regression/issue_00809/issue_00809_n.pat 0 → 100644
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
regression/issue_00809/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] x = 0;
wire y;
always @(posedge clk)
begin
x = x + 1;
end
reg [3:0] A;
reg [3:0] B;
wire [3:0] O;
wire [3:0] O_p;
wire C;
wire C_p;
assign {C_p, O_p} = A + B;
top uut (C,O,A,B);
assert_comb c_test (C,C_p);
assert_comb o0_test (O[0],O_p[0]);
assert_comb o1_test (O[1],O_p[1]);
assert_comb o2_test (O[2],O_p[2]);
assert_comb o3_test (O[3],O_p[3]);
endmodule
regression/issue_00814/issue_00814_fail.ys 0 → 100644
tee -o result.out read_verilog -formal ../top.v
regression/issue_00814/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] c = 0;
reg in, jmp = 0;
wire [8-1:0] out,out_o;
always @(posedge clk)
begin
c = c + 1;
end
assign in = c[0];
assign jmp = c[1];
initial out = 0;
always @(posedge clk)
if (jmp)
out <= { out[UNDEFINED-1:0], in };
else
out <= { 1'b0, out[UNDEFINED-1:1] };
top uut (clk, jmp, in, out_o);
assert_comb o0_test (out[0],out_o[0]);
assert_comb o1_test (out[1],out_o[1]);
assert_comb o2_test (out[2],out_o[2]);
assert_comb o3_test (out[3],out_o[3]);
assert_comb o4_test (out[4],out_o[4]);
assert_comb o5_test (out[5],out_o[5]);
assert_comb o6_test (out[6],out_o[6]);
assert_comb o7_test (out[7],out_o[7]);
endmodule
regression/issue_00823/issue_00823.ys 0 → 100644
read_ilang ../t2.ilang
synth -run coarse
regression/issue_00826/issue_00826.ys 0 → 100644
read_verilog ../top.v
synth
regression/issue_00831/issue_00831.pat 0 → 100644
yosys-smt2-memory rom 2 8 1 0 async
regression/issue_00831/issue_00831.ys 0 → 100644
read_verilog ../top.v
prep
write_smt2 result.out
regression/issue_00831/top.v
`default_nettype none
module A;
parameter P = 0;
endmodule
module top;
A inst_i();
defparam inst_i.P = 1;
module test(input [1:0] addr, output [7:0] o);
reg [7:0] rom [0:3];
initial begin
rom[0] <= 8'b 0100100x;
rom[1] <= 8'b 00100x01;
rom[2] <= 8'b 010x0010;
rom[3] <= 8'b 0x010100;
end
assign o = rom[addr];
endmodule
regression/issue_00835/issue_00835.ys 0 → 100644
read_verilog ../top.v
prep
select -assert-count 4 t:$dff
regression/scripts/issue_00126.ys → regression/issue_00857/issue_00857.ys
read_verilog ../top.v
synth -top top
write_verilog synth.v
select -assert-count 1 t:$_DFF_P_
select -assert-none t:$_DFF_P_ %% t:* %D
regression/issue_00865/issue_00865.ys 0 → 100644
read_verilog ../top.v
write_verilog temp.v
proc
opt
fsm
opt
memory
opt
synth_xilinx -top tc
select -assert-count 12 t:FDRE
regression/issue_00867/issue_00867.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -flatten
select -assert-count 1 t:RAMB36E1
regression/issue_00870/issue_00870.ys 0 → 100644
read_verilog ../top.v
hierarchy -auto-top -check;
proc; clean;
memory;
opt -full;
flatten;
write_verilog multimux_out_1.v
opt -full;
write_verilog multimux_out_2.v
delete;
read_verilog multimux_out_2.v
regression/issue_00873/issue_00873.ys 0 → 100644
read_verilog ../top.v
synth_xilinx
flatten
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:FDRE_1
regression/issue_00888/issue_00888.ys 0 → 100644
read_verilog -DBROKEN ../top.v
synth_xilinx
select -assert-count 4 t:FDRE
regression/issue_00896/issue_00896.ys 0 → 100644
read_verilog ../outreg.v
hierarchy -top dut
proc
memory -nomap
equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd dut
stat
select -assert-count 1 t:TRELLIS_DPR16X4
select -assert-count 4 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF t:TRELLIS_DPR16X4 %% t:* %D
regression/issue_00896/testbench.v deleted 100644 → 0
`include "../outreg.v"
module tb;
reg fast_clk, slow_clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, tb);
repeat (80) @(posedge slow_clk);
$display("OKAY");
$finish;
end
always #4 fast_clk = (fast_clk === 1'b0);
always #12 slow_clk = (slow_clk === 1'b0);
reg [7:0] wdata = 1;
always @(posedge fast_clk) wdata <= {wdata[6:0], wdata[7] ^ wdata[2]};
reg [3:0] waddr = 0;
always @(posedge fast_clk) waddr <= waddr + 1'b1;
reg [3:0] raddr = 0;
always @(posedge slow_clk) raddr <= raddr + 1'b1;
wire [3:0] rdata, rdata_postsyn;
dut dut_i(
.fast_clk(fast_clk), .slow_clk(slow_clk),
.raddr(raddr), .waddr(waddr), .wen(1'b1),
.wdata(wdata[3:0]), .rdata(rdata)
);
dut_syn dut_syn_i(
.fast_clk(fast_clk), .slow_clk(slow_clk),
.raddr(raddr), .waddr(waddr), .wen(1'b1),
.wdata(wdata[3:0]), .rdata(rdata_postsyn)
);
always @(posedge fast_clk)
if (rdata_postsyn != rdata) begin
$display("ERROR");
$finish;
end
endmodule
regression/issue_00922/issue_00922.ys 0 → 100644
read_verilog ../top.v
proc
memory_dff -nordff
memory_collect
opt_reduce
clean
write_firrtl firrtl.firrtl
regression/issue_00922/top.v
......@@ -16,11 +16,7 @@ module top
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
......@@ -34,11 +30,7 @@ module top
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......
regression/issue_00931/issue_00931.ys 0 → 100644
read_verilog ../top.v
prep
select -assert-none t:$dlatch
regression/issue_00935/issue_00935.ys 0 → 100644
read_verilog ../top.v
prep -top picorv32 -nordff
opt -fast
write_smt2 picorv32.smt2
regression/issue_00938/issue_00938.ys 0 → 100644
read_verilog ../top.v
proc
memory_dff -nordff
opt_reduce
clean
write_firrtl firrtl.firrtl
regression/issue_00938/top.v
......@@ -16,11 +16,7 @@ module top
// Port A
always @ (posedge clka)
begin
`ifndef BUG
if (we_a)
`else
if (we_b)
`endif
begin
ram[addr_a] <= data_a;
q_a <= data_a;
......@@ -34,11 +30,7 @@ module top
// Port B
always @ (posedge clkb)
begin
`ifndef BUG
if (we_b)
`else
if (we_a)
`endif
begin
ram[addr_b] <= data_b;
q_b <= data_b;
......
regression/issue_00940/issue_00940.ys 0 → 100644
read_verilog ../*.v
synth_ice40 -top SuperTopEntity -json TopEntity.json
regression/issue_00948/issue_00948.ys 0 → 100644
read_ilang ../bug.rtlil
synth
opt_expr
write_verilog bug.v
delete
read_verilog bug.v
regression/issue_00954/issue_00954.pat 0 → 100644
Eval result: \\out = 4'1000.
regression/issue_00954/issue_00954.ys 0 → 100644
read_verilog ../top.v
synth
abc
eval -set addr 24
aigmap
tee -a result.out eval -set addr 24
regression/issue_00955/issue_00955.pat 0 → 100644
Eval result: \\out = 8'00001000.
regression/issue_00955/issue_00955.ys 0 → 100644
read_verilog ../top.v
synth
tee -a result1.out eval -set addr 24
abc
tee -a result.out eval -set addr 24
regression/issue_00956/issue_00956.ys 0 → 100644
read_verilog ../top.v
tee -a result.log synth_ice40 -top inivalue
regression/issue_00961/issue_00961.ys 0 → 100644
read_verilog ../top.v
proc
regression/issue_00968/issue_00968.pat 0 → 100644
assign o_value = { 4'hx, i_value }
regression/issue_00968/issue_00968.ys 0 → 100644
read -sv ../top.v
hierarchy -top mcve1
synth
write_verilog result.out
regression/issue_00981/issue_00981.ys 0 → 100644
read_verilog ../top.v
tee -a result.out synth_ice40
regression/issue_00982/issue_00982.ys 0 → 100644
read_verilog ../top.v
synth_xilinx
select -assert-count 3 t:FDRE
tee -a result.out dump t:FDRE
regression/issue_00993/issue_00993.ys 0 → 100644
read -formal ../top.v
hierarchy -top top
synth
#write_verilog rtl_yosys.v
regression/issue_00997/issue_00997.pat 0 → 100644
reg \\reg10_reg\[0\] = 1'h0;
regression/issue_00997/issue_00997.ys 0 → 100644
read -formal ../top.v
hierarchy -top top
synth
write_verilog -noattr result.out
regression/issue_01002/issue_01002.pat 0 → 100644
Estimated number of LCs: 87
regression/issue_01002/issue_01002.ys 0 → 100644
read -sv ../top.v
hierarchy -top onehot -chparam LG 7
tee -a result.out synth_xilinx
regression/issue_01014/issue_01014.ys 0 → 100644
read_verilog ../top.v
synth
regression/issue_01016/issue_01016.ys 0 → 100644
read_verilog -sv ../top.v
proc
wreduce -keepdc
select -assert-count 1 t:$mux
regression/issue_01022/issue_01022.ys 0 → 100644
read_verilog -sv ../top.v
tee -a result.log dump
regression/issue_01023/issue_01023.ys 0 → 100644
read_verilog -icells ../top.v
techmap
regression/issue_01033/issue_01033.ys 0 → 100644
read_verilog ../top.v
synth_xilinx
select -assert-none t:RAM64X1D
regression/issue_01034/issue_01034.ys 0 → 100644
read_verilog -DUNPACKED ../top.v
synth_xilinx -nodram
select -assert-none t:FDRE
regression/issue_01040/issue_01040.pat 0 → 100644
.subckt dut_sub a\[2\]=a\[2\] a\[3\]=a\[3\] a\[4\]=a\[4\] a\[5\]=a\[5\] a\[6\]=a\[6\] a\[7\]=a\[7\] a\[8\]=a\[8\] a\[9\]=a\[9\] a\[10\]=a\[10\] a\[11\]=a\[11\] a\[12\]=a\[12\] a\[13\]=a\[13\] a\[14\]=a\[14\] a\[15\]=a\[15\] a\[16\]=a\[16\] a\[17\]=a\[17\] a\[18\]=a\[18\] a\[19\]=a\[19\] a\[20\]=a\[20\] a\[21\]=a\[21\] a\[22\]=a\[22\] a\[23\]=a\[23\] a\[24\]=a\[24\] a\[25\]=a\[25\] a\[26\]=a\[26\] a\[27\]=a\[27\] a\[28\]=a\[28\] a\[29\]=a\[29\] a\[30\]=a\[30\] a\[31\]=a\[31\] a\[32\]=a\[32\] a_l\[2\]=a_l\[2\] a_l\[3\]=a_l\[3\] a_l\[4\]=a_l\[4\] a_l\[5\]=a_l\[5\] a_l\[6\]=a_l\[6\] a_l\[7\]=a_l\[7\] a_l\[8\]=a_l\[8\] a_l\[9\]=a_l\[9\] a_l\[10\]=a_l\[10\] a_l\[11\]=a_l\[11\] a_l\[12\]=a_l\[12\] a_l\[13\]=a_l\[13\] a_l\[14\]=a_l\[14\] a_l\[15\]=a_l\[15\] a_l\[16\]=a_l\[16\] a_l\[17\]=a_l\[17\] a_l\[18\]=a_l\[18\] a_l\[19\]=a_l\[19\] a_l\[20\]=a_l\[20\] a_l\[21\]=a_l\[21\] a_l\[22\]=a_l\[22\] a_l\[23\]=a_l\[23\] a_l\[24\]=a_l\[24\] a_l\[25\]=a_l\[25\] a_l\[26\]=a_l\[26\] a_l\[27\]=a_l\[27\] a_l\[28\]=a_l\[28\] a_l\[29\]=a_l\[29\] a_l\[30\]=a_l\[30\] a_l\[31\]=a_l\[31\] a_l\[32\]=a_l\[32\] clk=clk
regression/issue_01040/issue_01040.ys 0 → 100644
read_verilog ../top.v
synth
write_blif result.out
regression/issue_01047/issue_01047.ys 0 → 100644
read -formal ../top.v
hierarchy -top top
synth
select -assert-count 1 t:$_NOR_
select -assert-none t:$_NOR_ %% t:* %D
regression/issue_01063/issue_01063_fail.pat 0 → 100644
ERROR: Gate cell u_mid8 not found in module top.
regression/issue_01063/issue_01063_fail.ys 0 → 100644
read_verilog ../top.v
proc
fmcombine top u_mid1 u_mid8
regression/issue_01065/issue_01065.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.out opt -fast
regression/issue_01065/issue_01065_n.ys 0 → 100644
Warning: Driver-driver conflict for \\q between cell u.i and constant 1'0 in top: Resolved using constant.
regression/issue_01070/issue_01070.ys 0 → 100644
read_verilog ../top.v
proc
dff2dffe
simplemap
opt
opt_rmdff
select -assert-count 1 t:$_DFF_N_
select -assert-none t:$_DFF_N_ %% t:* %D
regression/issue_01091/issue_01091.ys 0 → 100644
read_verilog ../top.v
proc
opt
techmap
muxcover -nopartial
select -assert-count 1 t:$_MUX4_
select -assert-none t:$_MUX4_ %% t:* %D
regression/issue_01093/issue_01093_fail.pat 0 → 100644
ERROR: Design has no top module, use the 'hierarchy' command to specify one.
regression/issue_01093/issue_01093_fail.ys 0 → 100644
read_verilog ../top.v
proc
sim
regression/issue_01093/top.v
......@@ -10,7 +10,6 @@ module top
parameter X = 1;
wire o;
`ifndef BUG
always @(posedge cin)
A <= o;
......@@ -18,9 +17,6 @@ always @(posedge cin)
middle u_mid (.x(x),.o(o));
u_rtl inst_u_rtl (.x(x),.o(o));
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
......
regression/issue_01115/issue_01115.pat 0 → 100644
connect \\\o 33'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
regression/issue_01115/issue_01115.ys 0 → 100644
read_verilog ../top.v
proc
tee -o result.out dump
regression/issue_01126/issue_01126.ys 0 → 100644
read_verilog ../top.v
write_verilog result.out
#write_json test_synth.json
regression/issue_01128/issue_01128.ys 0 → 100644
read_verilog ../top.v
insbuf
# select just the $_BUF_ from w1 to w2 as @buf
select -set buf w:w1 %coe1 w:w1 %d
# set the keep attribute for the $_BUF_ from w1 to w2
setattr -set keep 1 @buf
opt_clean
select -assert-count 1 t:$_BUF_
regression/issue_01131/issue_01131_fail.pat 0 → 100644
ERROR: Value conversion failed:
regression/issue_01132/issue_01132.ys 0 → 100644
read_verilog ../top.v
proc; opt; wreduce; simplemap; muxcover -mux4=150
select -assert-count 1 t:$_MUX4_
regression/issue_01135/issue_01135.ys 0 → 100644
read_verilog ../top.v
proc; pmux2shiftx -norange; opt -full
select -assert-count 1 t:$pmux
select -assert-count 3 t:$eq
regression/issue_01145/issue_01145.ys 0 → 100644
read_verilog -sv ../top.sv
hierarchy -check -top TopModule
proc
flatten
regression/issue_01161/issue_01161.ys 0 → 100644
read_verilog ../top.v
hierarchy
proc
write_verilog result_no_opt.log
equiv_opt -assert opt_clean
opt_clean
write_verilog result.out
regression/scripts/issue_00432.ys → regression/issue_01193/issue_01193.ys
read_verilog -sv ../top.v
proc
hierarchy -check
synth -top top
write_verilog synth.v
select -assert-count 0 t:$dlatch
regression/issue_01206/issue_01206.ys 0 → 100644
read_ilang ../top.il
proc_init
regression/scripts/issue_00160.ys → regression/issue_01216/issue_01216.ys
read_verilog ../top.v
synth_ice40 -top top
write_verilog synth.v
write_blif test.blif
regression/issue_01217/issue_01217.ys 0 → 100644
tee -o result.out read_verilog ../top.v
regression/issue_01220/issue_01220.ys 0 → 100644
read_verilog ../top.v
hierarchy -top top
proc
flatten
regression/issue_01223/issue_01223.ys 0 → 100644
read_verilog ../top.v
synth_xilinx
regression/issue_01225/issue_01225.ys 0 → 100644
read_verilog ../top.v
synth_xilinx
select -assert-count 1 t:BUFT
regression/issue_01243/issue_01243.ys 0 → 100644
read_verilog ../top.v
synth
write_verilog -noattr result.out
regression/scripts/issue_00134.ys → regression/issue_01259/issue_01259.ys
read_verilog ../top.v
hierarchy -top top
proc; opt; memory; dff2dffe; wreduce; clean; opt
write_verilog -noexpr -norename synth.v
write_smt2
regression/scripts/issue_00102.ys → regression/issue_01273/issue_01273.ys
read_verilog ../top.v
synth -top top
write_verilog synth.v
muxcover -mux8
select -assert-count 9 t:$_MUX8_
regression/issue_01284/issue_01284.ys 0 → 100644
read_verilog ../top.v
proc
synth -top top
equiv_opt -assert extract_fa -ha -v
design -load postopt
cd top
select -assert-count 1 t:$_ANDNOT_
select -assert-count 1 t:$_AND_
select -assert-count 2 t:$_NOT_
select -assert-count 1 t:$_OR_
select -assert-count 2 t:$_XNOR_
select -assert-count 2 t:$fa
select -assert-none t:$_ANDNOT_ t:$_AND_ t:$_NOT_ t:$_OR_ t:$_XNOR_ t:$fa %% t:* %D
regression/issue_01284/testbench.v deleted 100644 → 0
module testbench;
reg [2:0] in;
wire patt_out,out;
wire patt_carry_out,carryout;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#5 in = 0;
repeat (10000) begin
#5 in = in + 1;
end
$display("OKAY");
end
top uut (
.x(in[0]),
.y(in[1]),
.cin(in[2]),
.A(out),
.cout(carryout)
);
assign {patt_carry_out,patt_out} = in[2] + in[1] + in[0];
assert_comb out_test(.A(patt_out), .B(out));
assert_comb carry_test(.A(patt_carry_out), .B(carryout));
endmodule
regression/issue_01284/top.v
......@@ -8,10 +8,6 @@ module top
output cout
);
`ifndef BUG
assign {cout,A} = cin + y + x;
`else
assign {cout,A} = cin - y * x;
`endif
endmodule
regression/issue_01291/issue_01291.ys 0 → 100644
read_verilog ../top.v
proc
equiv_opt -assert prep
prep -top frozen
tee -o result.out dump
write_verilog top.v
regression/issue_01329/issue_01329.ys 0 → 100644
# read design
read_verilog ../dff.v
read_verilog -sv ../synchronizer.sv
hierarchy -check
# high-level synthesis
proc; opt; fsm; opt; memory; opt
flatten
cd dff # Constrain all select calls below inside the top module
select -assert-count 4 t:$adff
select -assert-count 1 t:$mux
select -assert-none t:$adff t:$mux %% t:* %D
regression/issue_01360/issue_01360.ys 0 → 100644
read_verilog -sv ../top.v
synth_ice40 -blif out.blif
regression/scripts/issue_00481.ys → regression/issue_01364/issue_01364.ys
read_verilog ../top.v
synth_ice40 -blif tlt.blif -top top
write_verilog synth.v
regression/issue_01372/issue_01372.ys 0 → 100644
read -define BROKEN_CODE
read -formal ../top.v
prep -top mcvesix
tee -o result.log equiv_opt -assert prep # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mcvesix # Constrain all select calls below inside the top module
select -assert-count 2 w:k s:32
regression/run.sh
......@@ -2,7 +2,7 @@
set -x
test -d $1
test -f scripts/$2.ys
test -f $2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
......@@ -10,232 +10,48 @@ cd $1/work_$2
touch .start
# cases where 'syntax error' or other errors are expected
if [ "$1" = "issue_00089" ] ||\
[ "$1" = "issue_00093" ] ||\
[ "$1" = "issue_00095" ] ||\
[ "$1" = "issue_00096" ] ||\
[ "$1" = "issue_00196" ] ||\
[ "$1" = "issue_00362" ] ||\
[ "$1" = "issue_00582" ] ||\
[ "$1" = "issue_00594" ] ||\
[ "$1" = "issue_00603" ] ||\
[ "$1" = "issue_00635" ] ||\
[ "$1" = "issue_00639" ] ||\
[ "$1" = "issue_00763" ] ||\
[ "$1" = "issue_00814" ] ||\
[ "$1" = "issue_01063" ] ||\
[ "$1" = "issue_01093" ] ||\
[ "$1" = "issue_01131" ] ||\
[ "$1" = "issue_01144" ]; then
expected_string="syntax error"
#Change checked string for check other errors
if [ "$1" = "issue_00196" ]; then
expected_string="Found posedge/negedge event"
elif [ "$1" = "issue_00362" ]; then
expected_string="is connected to constants:"
elif [ "$1" = "issue_00582" ]; then
expected_string="Failed to detect width for identifier"
elif [ "$1" = "issue_00594" ]; then
expected_string="Single range expected"
elif [ "$1" = "issue_00639" ]; then
expected_string="ERROR: Found 3 unproven \$equiv cells in 'equiv_status -assert'."
elif [ "$1" = "issue_00763" ]; then
expected_string="Invalid nesting"
elif [ "$1" = "issue_00814" ]; then
expected_string="is implicitly declared"
elif [ "$1" = "issue_01063" ]; then
expected_string="Gate cell u_mid8 not found in module top."
elif [ "$1" = "issue_01093" ]; then
expected_string="ERROR: Design has no top module, use the 'hierarchy' command to specify one."
elif [ "$1" = "issue_01131" ]; then
expected_string="ERROR: Value conversion failed"
fi
if yosys -ql yosys.log ../../scripts/$2.ys; then
#
if [[ $2 =~ "_fail" ]]; then
#4 - An error expected
if yosys -ql yosys.log ../$2.ys; then
echo FAIL > ${1}_${2}.status
else
if grep "$expected_string" yosys.log; then
if [ -f "../$2.pat" ]; then
expectation=$(<../$2.pat)
if grep "$expectation" yosys.log; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
fi
# cases without any additional checks (only checks in .ys script)
elif [ "$1" = "issue_00502" ] ||\
[ "$1" = "issue_00524" ] ||\
[ "$1" = "issue_00527" ] ||\
[ "$1" = "issue_00642" ] ||\
[ "$1" = "issue_00644" ] ||\
[ "$1" = "issue_00655" ] ||\
[ "$1" = "issue_00675" ] ||\
[ "$1" = "issue_00685" ] ||\
[ "$1" = "issue_00689" ] ||\
[ "$1" = "issue_00699" ] ||\
[ "$1" = "issue_00708" ] ||\
[ "$1" = "issue_00774" ] ||\
[ "$1" = "issue_00781" ] ||\
[ "$1" = "issue_00785" ] ||\
[ "$1" = "issue_00810" ] ||\
[ "$1" = "issue_00823" ] ||\
[ "$1" = "issue_00826" ] ||\
[ "$1" = "issue_00831" ] ||\
[ "$1" = "issue_00835" ] ||\
[ "$1" = "issue_00857" ] ||\
[ "$1" = "issue_00862" ] ||\
[ "$1" = "issue_00865" ] ||\
[ "$1" = "issue_00867" ] ||\
[ "$1" = "issue_00870" ] ||\
[ "$1" = "issue_00873" ] ||\
[ "$1" = "issue_00888" ] ||\
[ "$1" = "issue_00922" ] ||\
[ "$1" = "issue_00931" ] ||\
[ "$1" = "issue_00935" ] ||\
[ "$1" = "issue_00938" ] ||\
[ "$1" = "issue_00940" ] ||\
[ "$1" = "issue_00948" ] ||\
[ "$1" = "issue_00961" ] ||\
[ "$1" = "issue_00981" ] ||\
[ "$1" = "issue_00987" ] ||\
[ "$1" = "issue_00993" ] ||\
[ "$1" = "issue_01016" ] ||\
[ "$1" = "issue_01033" ] ||\
[ "$1" = "issue_01034" ] ||\
[ "$1" = "issue_01047" ] ||\
[ "$1" = "issue_01070" ] ||\
[ "$1" = "issue_01091" ] ||\
[ "$1" = "issue_01128" ] ||\
[ "$1" = "issue_01132" ] ||\
[ "$1" = "issue_01135" ] ||\
[ "$1" = "issue_01145" ] ||\
[ "$1" = "issue_01220" ] ||\
[ "$1" = "issue_01223" ] ||\
[ "$1" = "issue_01231" ] ||\
[ "$1" = "issue_01273" ] ||\
[ "$1" = "issue_01329" ] ||\
[ "$1" = "issue_01364" ] ||\
[ "$1" = "issue_01372" ] ||\
[ "$1" = "issue_00623" ] ||\
[ "$1" = "issue_00656" ] ||\
[ "$1" = "issue_01014" ] ||\
[ "$1" = "issue_01023" ] ||\
[ "$1" = "issue_01084" ] ||\
[ "$1" = "issue_01193" ] ||\
[ "$1" = "issue_01206" ] ||\
[ "$1" = "issue_01216" ] ||\
[ "$1" = "issue_01225" ] ||\
[ "$1" = "issue_01259" ] ||\
[ "$1" = "issue_01360" ]; then
yosys -ql yosys.log ../../scripts/$2.ys;
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
else
echo PASS > ${1}_${2}.status
fi
# cases where some object names are/aren't expected in output file (tee -o result.log in the test script)
elif [ "$1" = "issue_00737" ] ||\
[ "$1" = "issue_00954" ] ||\
[ "$1" = "issue_00955" ] ||\
[ "$1" = "issue_00956" ] ||\
[ "$1" = "issue_00968" ] ||\
[ "$1" = "issue_00982" ] ||\
[ "$1" = "issue_00997" ] ||\
[ "$1" = "issue_01002" ] ||\
[ "$1" = "issue_01022" ] ||\
[ "$1" = "issue_01040" ] ||\
[ "$1" = "issue_01065" ] ||\
[ "$1" = "issue_01115" ] ||\
[ "$1" = "issue_01118" ] ||\
[ "$1" = "issue_01243" ] ||\
[ "$1" = "issue_00329" ] ||\
[ "$1" = "issue_01126" ] ||\
[ "$1" = "issue_01161" ] ||\
[ "$1" = "issue_01217" ] ||\
[ "$1" = "issue_01291" ]; then
expected_string=""
expected="1"
if [ "$1" = "issue_00737" ]; then
expected_string="ATTR \\\A:"
elif [ "$1" = "issue_00954" ]; then
expected_string="out = 4'1000"
elif [ "$1" = "issue_00955" ]; then
expected_string="out = 8'00001000"
elif [ "$1" = "issue_00956" ]; then
expected_string="Wire inivalue.r_val has an unprocessed 'init' attribute"
expected="0"
elif [ "$1" = "issue_00968" ]; then
expected_string="assign o_value = { 4'hx, i_value }"
elif [ "$1" = "issue_00982" ]; then
expected_string="INIT 1'0"
elif [ "$1" = "issue_00997" ]; then
expected_string="h0"
elif [ "$1" = "issue_01002" ]; then
expected_string="Estimated number of LCs: 87"
elif [ "$1" = "issue_01022" ]; then
expected_string="connect \\\b 32'11111111111111111111111111111111"
elif [ "$1" = "issue_01040" ]; then
expected_string=".subckt dut_sub a\[2\]=a\[2\] a\[3\]=a\[3\] a\[4\]=a\[4\] a\[5\]=a\[5\] a\[6\]=a\[6\]"
elif [ "$1" = "issue_01065" ]; then
expected_string="Driver-driver conflict for"
expected="0"
elif [ "$1" = "issue_01115" ]; then
expected_string="connect \\\o 33'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx"
elif [ "$1" = "issue_01118" ]; then
expected_string="connect \\\o \[0\] 1'0"
elif [ "$1" = "issue_01126" ]; then
expected_string="assign d = c\\[5:0\\]"
elif [ "$1" = "issue_01243" ]; then
expected_string="assign y = reg_assign;"
elif [ "$1" = "issue_00329" ]; then
expected_string="wire \\[-1"
expected="0"
elif [ "$1" = "issue_01161" ]; then
expected_string="assign z0 = b"
elif [ "$1" = "issue_01217" ]; then
expected_string="is implicitly declared."
expected="0"
elif [ "$1" = "issue_01291" ]; then
expected_string="connect \\\out 1'x"
expected="0"
fi
if [ "$1" = "issue_01118" ]; then
# This issue manifests as an infinite loop.
timeout 5s yosys -ql yosys.log ../../scripts/$2.ys;
else
yosys -ql yosys.log ../../scripts/$2.ys;
fi
else
#2 - All asserts in .ys script
yosys -ql yosys.log ../$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if grep "$expected_string" result.log; then
if [ $expected = "1" ]; then
else
#3 Output log check
if [ -f "../$2.pat" ]; then # Expected behavior
expectation=$(<../$2.pat)
if grep "$expectation" result.out; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
else
if [ $expected = "1" ]; then
elif [ -f "../$2_n.pat" ]; then # Not expected behavior
expectation=$(<../$2_n.pat)
if grep "$expectation" result.out; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
fi
# cases with simulation checks
else
#1 Iverilog run when testbench exists
elif [ -f "../testbench.v" ]; then
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
TECHLIBS_PREFIX=../../../../../techlibs
......@@ -243,43 +59,17 @@ else
COMMON_PREFIX=/usr/local/share/yosys
TECHLIBS_PREFIX=/usr/local/share/yosys
fi
if [ -f "../iverilog_adds.txt" ]; then
iverilog_adds=$(<../iverilog_adds.txt)
else
iverilog_adds=""
#Additional sources for iverilog simulation
if [ "$1" = "issue_00160" ] ||\
[ "$1" = "issue_00182" ] ||\
[ "$1" = "issue_00183" ] ||\
[ "$1" = "issue_00481" ] ||\
[ "$1" = "issue_00567" ] ||\
[ "$1" = "issue_00589" ] ||\
[ "$1" = "issue_00628" ]; then
iverilog_adds="$TECHLIBS_PREFIX/ice40/cells_sim.v"
elif [ "$1" = "issue_00896" ]; then
iverilog_adds="$TECHLIBS_PREFIX/ecp5/cells_sim.v"
fi
yosys -ql yosys.log ../../scripts/$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
# cases where we do not run iverilog
if [ "$1" = "issue_00449" ] ||\
[ "$1" = "issue_00084" ]; then
echo PASS > ${1}_${2}.status
touch .stamp
exit 0
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v $iverilog_adds
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
......@@ -288,8 +78,9 @@ else
else
echo PASS > ${1}_${2}.status
fi
else
echo PASS > ${1}_${2}.status
fi
fi
fi
touch .stamp
regression/scripts/issue_00018.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
select -assert-any w:*i
write_verilog synth.v
regression/scripts/issue_00067.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00071.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00081.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00082.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00083.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00085.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00086.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00253.ys deleted 100644 → 0
read_verilog ../top.v
proc; opt; fsm -encoding binary
techmap; opt; stat
write_verilog synth.v
regression/scripts/issue_00282.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
#synth_ice40 -blif litescope.bli -top top
write_verilog synth.v
regression/scripts/issue_00350.ys deleted 100644 → 0
read_verilog -sv ../top.v
synth -top top
abc -clk clk -g AND
opt
write_verilog synth.v
regression/scripts/issue_00444.ys deleted 100644 → 0
read_verilog -formal ../top.v
hierarchy
proc_prune
proc_init
proc_mux
proc_dff
proc_clean
opt_clean
opt_merge
opt_rmdff
opt_clean
opt_expr
opt_rmdff
memory
synth -top top
write_verilog synth.v
regression/scripts/issue_00474.ys deleted 100644 → 0
read_verilog -formal ../top.v
verilog_defaults -push
verilog_defaults -pop
synth -top top
write_verilog synth.v
regression/scripts/issue_00644.ys deleted 100644 → 0
tee -o result.log read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00656.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_00689.ys deleted 100644 → 0
tee -o result.log read_verilog -formal ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00699.ys deleted 100644 → 0
tee -o result.log read_verilog -sv ../top.v
regression/scripts/issue_00705.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00708.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_00737.ys deleted 100644 → 0
tee -o result.log read_verilog -dump_ast1 ../top.v
regression/scripts/issue_00763.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00790.ys deleted 100644 → 0
read -formal ../top_assert.v
prep -top mcve
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00814.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00823.ys deleted 100644 → 0
read_ilang ../t2.ilang
synth -run coarse
tee -o result.log write_verilog synth.v
regression/scripts/issue_00826.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_00831.ys deleted 100644 → 0
read_verilog ../top.v
prep
tee -o result.log write_smt2 test.smt2
regression/scripts/issue_00835.ys deleted 100644 → 0
read_verilog ../top.v
prep
select -assert-count 4 t:$dff
regression/scripts/issue_00857.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
select -assert-count 1 t:$_DFF_P_
select -assert-none t:$_DFF_P_ %% t:* %D
regression/scripts/issue_00862.ys deleted 100644 → 0
tee -o result.log read_verilog -sv ../top.v
regression/scripts/issue_00865.ys deleted 100644 → 0
read_verilog ../top.v
write_verilog temp.v
proc
opt
fsm
opt
memory
opt
synth_xilinx -top tc
select -assert-count 12 t:FDRE
regression/scripts/issue_00867.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -flatten
select -assert-count 1 t:RAMB36E1
regression/scripts/issue_00870.ys deleted 100644 → 0
read_verilog ../top.v
hierarchy -auto-top -check;
proc; clean;
memory;
opt -full;
flatten;
write_verilog multimux_out_1.v
opt -full;
write_verilog multimux_out_2.v
delete;
tee -o result.log read_verilog multimux_out_2.v
regression/scripts/issue_00873.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
flatten
stat
select -assert-count 1 t:BUFG
select -assert-count 1 t:FDRE
select -assert-count 1 t:FDRE_1
regression/scripts/issue_00888.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
select -assert-count 4 t:FDRE
regression/scripts/issue_00896.ys deleted 100644 → 0
read_verilog ../outreg.v
synth_ecp5
rename dut dut_syn
write_verilog -norename synth.v
regression/scripts/issue_00922.ys deleted 100644 → 0
read_verilog ../top.v
proc
memory_dff -nordff
memory_collect
opt_reduce
clean
write_firrtl firrtl.firrtl
regression/scripts/issue_00931.ys deleted 100644 → 0
read_verilog ../top.v
prep
select -assert-none t:$dlatch
regression/scripts/issue_00935.ys deleted 100644 → 0
read_verilog ../top.v
prep -top picorv32 -nordff
opt -fast
write_smt2 picorv32.smt2
regression/scripts/issue_00938.ys deleted 100644 → 0
read_verilog ../top.v
proc
memory_dff -nordff
opt_reduce
clean
write_firrtl firrtl.firrtl
regression/scripts/issue_00940.ys deleted 100644 → 0
read_verilog ../*.v
synth_ice40 -top SuperTopEntity -json TopEntity.json
regression/scripts/issue_00948.ys deleted 100644 → 0
read_ilang ../bug.rtlil
synth
opt_expr
write_verilog bug.v
delete
tee -a result.log read_verilog bug.v
regression/scripts/issue_00954.ys deleted 100644 → 0
read_verilog ../top.v
synth
abc
eval -set addr 24
aigmap
tee -a result.log eval -set addr 24
regression/scripts/issue_00955.ys deleted 100644 → 0
read_verilog ../top.v
synth
eval -set addr 24
abc
tee -a result.log eval -set addr 24
regression/scripts/issue_00956.ys deleted 100644 → 0
read_verilog ../top.v
tee -a result.log synth_ice40 -top inivalue
regression/scripts/issue_00961.ys deleted 100644 → 0
read_verilog ../top.v
tee -a result.log proc
regression/scripts/issue_00968.ys deleted 100644 → 0
read -sv ../top.v
hierarchy -top mcve1
synth
write_verilog result.log
regression/scripts/issue_00981.ys deleted 100644 → 0
read_verilog ../top.v
tee -a result.log synth_ice40
regression/scripts/issue_00982.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
tee -a result.log dump t:FDRE
regression/scripts/issue_00987.ys deleted 100644 → 0
tee -a result.log read_verilog -sv ../top.v
regression/scripts/issue_00993.ys deleted 100644 → 0
read -formal ../top.v
hierarchy -top top
tee -a result.log synth
#write_verilog rtl_yosys.v
regression/scripts/issue_00997.ys deleted 100644 → 0
read -formal ../top.v
hierarchy -top top
synth
write_verilog -noattr result.log
regression/scripts/issue_01002.ys deleted 100644 → 0
read -sv ../top.v
hierarchy -top onehot -chparam LG 7
tee -a result.log synth_xilinx
regression/scripts/issue_01016.ys deleted 100644 → 0
read_verilog -sv ../top.v
proc
wreduce -keepdc
select -assert-count 1 t:$mux
regression/scripts/issue_01022.ys deleted 100644 → 0
read_verilog -sv ../top.v
tee -a result.log dump
regression/scripts/issue_01023.ys deleted 100644 → 0
read_verilog -icells ../top.v
tee -a result.log techmap
regression/scripts/issue_01033.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
select -assert-none t:RAM64X1D
regression/scripts/issue_01034.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -nodram
select -assert-none t:FDRE
regression/scripts/issue_01040.ys deleted 100644 → 0
read_verilog ../top.v
synth
write_blif result.log
regression/scripts/issue_01047.ys deleted 100644 → 0
read -formal ../top.v
hierarchy -top top
synth
select -assert-count 1 t:$_NOR_
select -assert-none t:$_NOR_ %% t:* %D
regression/scripts/issue_01063.ys deleted 100644 → 0
read_verilog ../top.v
proc
fmcombine top u_mid1 u_mid8
regression/scripts/issue_01065.ys deleted 100644 → 0
read_verilog ../top.v
proc
tee -o result.log opt -fast
regression/scripts/issue_01070.ys deleted 100644 → 0
read_verilog ../top.v
proc
dff2dffe
simplemap
opt
opt_rmdff
select -assert-count 1 t:$_DFF_N_
select -assert-none t:$_DFF_N_ %% t:* %D
regression/scripts/issue_01084.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_01091.ys deleted 100644 → 0
read_verilog ../top.v
proc
opt
techmap
muxcover -nopartial
stat
select -assert-count 1 t:$_MUX4_
select -assert-none t:$_MUX4_ %% t:* %D
regression/scripts/issue_01093.ys deleted 100644 → 0
read_verilog ../top.v
proc
tee -o result.log sim
regression/scripts/issue_01115.ys deleted 100644 → 0
read_verilog ../top.v
proc
tee -o result.log dump
regression/scripts/issue_01118.ys deleted 100644 → 0
read_verilog ../top.v
proc
tee -o result.log dump
regression/scripts/issue_01126.ys deleted 100644 → 0
read_verilog ../top.v
write_verilog result.log
#write_json test_synth.json
regression/scripts/issue_01128.ys deleted 100644 → 0
read_verilog ../top.v
insbuf
# select just the $_BUF_ from w1 to w2 as @buf
select -set buf w:w1 %coe1 w:w1 %d
# set the keep attribute for the $_BUF_ from w1 to w2
setattr -set keep 1 @buf
opt_clean
select -assert-count 1 t:$_BUF_
regression/scripts/issue_01131.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_01132.ys deleted 100644 → 0
read_verilog ../top.v
proc; opt; wreduce; simplemap; muxcover -mux4=150
select -assert-count 1 t:$_MUX4_
regression/scripts/issue_01135.ys deleted 100644 → 0
read_verilog ../top.v
proc; pmux2shiftx -norange; opt -full
select -assert-count 1 t:$pmux
select -assert-count 3 t:$eq
regression/scripts/issue_01144.ys deleted 100644 → 0
read_verilog ../top.v
tee -o result.log stat
regression/scripts/issue_01145.ys deleted 100644 → 0
read_verilog -sv ../top.sv
hierarchy -check -top TopModule
proc
flatten
regression/scripts/issue_01161.ys deleted 100644 → 0
read_verilog ../top.v
hierarchy
proc
write_verilog result_no_opt.log
equiv_opt -assert opt_clean
opt_clean
write_verilog result.log
regression/scripts/issue_01193.ys deleted 100644 → 0
read_verilog -sv ../top.v
proc
select -assert-count 0 t:$dlatch
tee -o result.log dump
regression/scripts/issue_01206.ys deleted 100644 → 0
read_ilang ../top.il
tee -o result.log proc_init
regression/scripts/issue_01216.ys deleted 100644 → 0
read_verilog ../top.v
tee -o result.log synth_ice40 -top top
tee -o result.log write_blif test.blif
regression/scripts/issue_01217.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
regression/scripts/issue_01220.ys deleted 100644 → 0
read_verilog ../top.v
hierarchy -top top
proc
flatten
regression/scripts/issue_01223.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
regression/scripts/issue_01225.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx
select -assert-count 1 t:BUFT
regression/scripts/issue_01241.ys deleted 100644 → 0
read_verilog ../top.v
synth
write_verilog -noattr result.log
regression/scripts/issue_01243.ys deleted 100644 → 0
read_verilog ../top.v
synth
write_verilog -noattr result.log
regression/scripts/issue_01259.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
hierarchy -top top
tee -o result.log write_smt2
regression/scripts/issue_01273.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
muxcover -mux8
select -assert-count 9 t:$_MUX8_
regression/scripts/issue_01284.ys deleted 100644 → 0
read_verilog ../top.v
proc
synth -top top
extract_fa -ha -v
tee -o result.log dump
synth -top top
write_verilog synth.v
regression/scripts/issue_01291.ys deleted 100644 → 0
tee -o result.log read_verilog ../top.v
proc
equiv_opt -assert prep
prep -top frozen
tee -o result.log dump
regression/scripts/issue_01329.ys deleted 100644 → 0
# read design
read_verilog ../dff.v
read_verilog -sv ../synchronizer.sv
hierarchy -check
# high-level synthesis
proc; opt; fsm; opt; memory; opt
flatten
cd dff # Constrain all select calls below inside the top module
select -assert-count 4 t:$adff
select -assert-count 1 t:$mux
select -assert-none t:$adff t:$mux %% t:* %D
regression/scripts/issue_01360.ys deleted 100644 → 0
read_verilog -sv ../top.v
synth_ice40 -blif out.blif
regression/scripts/issue_01372.ys deleted 100644 → 0
read -define BROKEN_CODE
read -formal ../top.v
prep -top mcvesix
tee -o result.log equiv_opt -assert prep # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mcvesix # Constrain all select calls below inside the top module
select -assert-count 2 w:k s:32
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