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yosys-tests
Unverified Commit 13009106 by Miodrag Milanović Committed by GitHub
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Merge pull request #75 from SergeyDegtyar/test_changes_in_yosys-test_3 

The third variant of changes in yosys-tests
parents e9bff780 a965148e
Showing with 224 additions and 1352 deletions
regression/Makefile
......@@ -17,9 +17,6 @@ clean::
))
endef
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00018
$(eval $(call template,issue_00018,issue_00018))
......@@ -30,9 +27,7 @@ $(eval $(call template,issue_00041,issue_00041))
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,issue_00065,issue_00065))
endif
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
......@@ -52,7 +47,7 @@ $(eval $(call template,issue_00081,issue_00081))
#Parsing Verilog input from `top_fault.v' to AST representation.
#top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
#
$(eval $(call template,issue_00082,issue_00082))
$(eval $(call template,issue_00082,issue_00082_fail))
#issue_00083
#Warning: Deep recursion in AST simplifier.
......@@ -60,7 +55,7 @@ $(eval $(call template,issue_00082,issue_00082))
#run.sh: line 21: 17264 Segmentation fault (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
#make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
#
$(eval $(call template,issue_00083,issue_00083))
$(eval $(call template,issue_00083,issue_00083_fail))
#issue_00084
$(eval $(call template,issue_00084,issue_00084))
......@@ -75,25 +70,25 @@ $(eval $(call template,issue_00086,issue_00086))
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
$(eval $(call template,issue_00089,issue_00089))
$(eval $(call template,issue_00089,issue_00089_fail))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
$(eval $(call template,issue_00093,issue_00093))
$(eval $(call template,issue_00093,issue_00093_fail))
#issue_00095
$(eval $(call template,issue_00095,issue_00095))
$(eval $(call template,issue_00095,issue_00095_fail))
#issue_00096
$(eval $(call template,issue_00096,issue_00096))
$(eval $(call template,issue_00096,issue_00096_fail))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
#issue_00099
$(eval $(call template,issue_00099,issue_00099))
$(eval $(call template,issue_00099,issue_00099_fail))
#issue_00102
$(eval $(call template,issue_00102,issue_00102))
......@@ -150,7 +145,7 @@ $(eval $(call template,issue_00194,issue_00194))
$(eval $(call template,issue_00195,issue_00195))
#issue_00196
$(eval $(call template,issue_00196,issue_00196))
$(eval $(call template,issue_00196,issue_00196_fail))
#issue_00210
$(eval $(call template,issue_00210,issue_00210))
......@@ -201,7 +196,7 @@ $(eval $(call template,issue_00350,issue_00350))
$(eval $(call template,issue_00361,issue_00361))
#issue_00362
$(eval $(call template,issue_00362,issue_00362))
$(eval $(call template,issue_00362,issue_00362_fail))
#issue_00372
$(eval $(call template,issue_00372,issue_00372))
......@@ -240,16 +235,16 @@ $(eval $(call template,issue_00527,issue_00527))
$(eval $(call template,issue_00567,issue_00567))
#issue_00582
$(eval $(call template,issue_00582,issue_00582))
$(eval $(call template,issue_00582,issue_00582_fail))
#issue_00589
$(eval $(call template,issue_00589,issue_00589))
#issue_00594
$(eval $(call template,issue_00594,issue_00594))
$(eval $(call template,issue_00594,issue_00594_fail))
#issue_00603
$(eval $(call template,issue_00603,issue_00603))
$(eval $(call template,issue_00603,issue_00603_fail))
#issue_00628
$(eval $(call template,issue_00628,issue_00628))
......@@ -258,10 +253,10 @@ $(eval $(call template,issue_00628,issue_00628))
$(eval $(call template,issue_00630,issue_00630))
#issue_00635
$(eval $(call template,issue_00635,issue_00635))
$(eval $(call template,issue_00635,issue_00635_fail))
#issue_00639
$(eval $(call template,issue_00639,issue_00639))
$(eval $(call template,issue_00639,issue_00639_fail))
#issue_00642
$(eval $(call template,issue_00642,issue_00642))
......@@ -294,7 +289,7 @@ $(eval $(call template,issue_00708,issue_00708))
$(eval $(call template,issue_00737,issue_00737))
#issue_00763
$(eval $(call template,issue_00763,issue_00763))
$(eval $(call template,issue_00763,issue_00763_fail))
#issue_00767
$(eval $(call template,issue_00767,issue_00767))
......@@ -310,6 +305,9 @@ $(eval $(call template,issue_00781,issue_00781))
#issue_00785
$(eval $(call template,issue_00785,issue_00785))
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00807
$(eval $(call template,issue_00807,issue_00807))
......@@ -320,7 +318,7 @@ $(eval $(call template,issue_00809,issue_00809))
$(eval $(call template,issue_00810,issue_00810))
#issue_00814
$(eval $(call template,issue_00814,issue_00814))
$(eval $(call template,issue_00814,issue_00814_fail))
#issue_00823
$(eval $(call template,issue_00823,issue_00823))
......@@ -340,7 +338,7 @@ $(eval $(call template,issue_00857,issue_00857))
#issue_00862
$(eval $(call template,issue_00862,issue_00862))
#issue_00865 - test failed (should be ok after merge https://github.com/YosysHQ/yosys/pull/866)
#issue_00865
$(eval $(call template,issue_00865,issue_00865))
#issue_00867
......@@ -409,6 +407,9 @@ $(eval $(call template,issue_00997,issue_00997))
#issue_01002
$(eval $(call template,issue_01002,issue_01002))
#issue_01014
$(eval $(call template,issue_01014,issue_01014))
#issue_01016
$(eval $(call template,issue_01016,issue_01016))
......@@ -431,7 +432,7 @@ $(eval $(call template,issue_01040,issue_01040))
$(eval $(call template,issue_01047,issue_01047))
#issue_01063
$(eval $(call template,issue_01063,issue_01063))
$(eval $(call template,issue_01063,issue_01063_fail))
#issue_01065
$(eval $(call template,issue_01065,issue_01065))
......@@ -446,7 +447,7 @@ $(eval $(call template,issue_01084,issue_01084))
$(eval $(call template,issue_01091,issue_01091))
#issue_01093
$(eval $(call template,issue_01093,issue_01093))
$(eval $(call template,issue_01093,issue_01093_fail))
#issue_01115
$(eval $(call template,issue_01115,issue_01115))
......@@ -458,7 +459,7 @@ $(eval $(call template,issue_01118,issue_01118))
$(eval $(call template,issue_01128,issue_01128))
#issue_01131
$(eval $(call template,issue_01131,issue_01131))
$(eval $(call template,issue_01131,issue_01131_fail))
#issue_01132
$(eval $(call template,issue_01132,issue_01132))
......@@ -467,7 +468,7 @@ $(eval $(call template,issue_01132,issue_01132))
$(eval $(call template,issue_01135,issue_01135))
#issue_01144
$(eval $(call template,issue_01144,issue_01144))
$(eval $(call template,issue_01144,issue_01144_fail))
#issue_01145
$(eval $(call template,issue_01145,issue_01145))
......@@ -500,8 +501,6 @@ $(eval $(call template,issue_01364,issue_01364))
$(eval $(call template,issue_01372,issue_01372))
#Still open bugs (should be failed):
#issue_00329
$(eval $(call template,issue_00329,issue_00329))
......@@ -512,9 +511,6 @@ $(eval $(call template,issue_00623,issue_00623))
#issue_00656
$(eval $(call template,issue_00656,issue_00656))
#issue_01014
$(eval $(call template,issue_01014,issue_01014))
#issue_01126
$(eval $(call template,issue_01126,issue_01126))
......@@ -545,7 +541,4 @@ $(eval $(call template,issue_01291,issue_01291))
#issue_01360
$(eval $(call template,issue_01360,issue_01360))
.PHONY: all clean
regression/issue_00018/issue_00018.ys 0 → 100644
read_verilog ../top.v
synth -top d
regression/issue_00018/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00018/top.v
......@@ -4,41 +4,116 @@
`timescale 1ns/10ps
module top (
x,clk,rst,a
module d (
cos_z0,
sin_z0,
done,
z0,
start,
clock,
reset
);
// Sine and cosine computer.
//
// This module computes the sine and cosine of an input angle. The
// floating point numbers are represented as integers by scaling them
// up with a factor corresponding to the number of bits after the point.
//
// Ports:
// -----
// cos_z0: cosine of the input angle
// sin_z0: sine of the input angle
// done: output flag indicated completion of the computation
// z0: input angle
// start: input that starts the computation on a posedge
// clock: clock input
// reset: reset input
output x;
reg x;
input clk;
input rst;
input [1:0] a;
output signed [19:0] cos_z0;
reg signed [19:0] cos_z0;
output signed [19:0] sin_z0;
reg signed [19:0] sin_z0;
output done;
reg done;
input signed [19:0] z0;
input start;
input clock;
input reset;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR
reg [5-1:0] i;
reg [1-1:0] state;
reg signed [20-1:0] dz;
reg signed [20-1:0] dx;
reg signed [20-1:0] dy;
reg signed [20-1:0] y;
reg signed [20-1:0] x;
reg signed [20-1:0] z;
if (reset) begin
state = 1'b0;
cos_z0 <= 1;
sin_z0 <= 0;
done <= 1'b0;
x = 0;
y = 0;
z = 0;
i = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
case (state)
1'b0: begin
if (start) begin
x = 159188;
y = 0;
z = z0;
i = 0;
done <= 1'b0;
state = 1'b1;
end
end
default: begin
x = 0;
i = 0;
1'b1: begin
dx = $signed(y >>> $signed({1'b0, i}));
dy = $signed(x >>> $signed({1'b0, i}));
case (i)
0: dz = 205887;
1: dz = 121542;
2: dz = 64220;
3: dz = 32599;
4: dz = 16363;
5: dz = 8189;
6: dz = 4096;
7: dz = 2048;
8: dz = 1024;
9: dz = 512;
10: dz = 256;
11: dz = 128;
12: dz = 64;
13: dz = 32;
14: dz = 16;
15: dz = 8;
16: dz = 4;
17: dz = 2;
default: dz = 1;
endcase
if ((z >= 0)) begin
x = x - dx;
y = y + dy;
z = z - dz;
end
else begin
x = x + dx;
y = y - dy;
z = z + dz;
end
if ((i == (19 - 1))) begin
cos_z0 <= x;
sin_z0 <= y;
state = 1'b0;
done <= 1'b1;
end
else begin
i = i + 1;
end
end
endcase
end
......
regression/issue_00041/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/scripts/issue_00059.ys → regression/issue_00059/issue_00059.ys
read_verilog ../top.v
#Myname: added some comment with a colon
synth -top top
write_verilog synth.v
regression/issue_00059/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00065/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00067/issue_00067.ys 0 → 100644
read_verilog ../top.v
freduce
regression/issue_00067/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00067/top.v
module top(b,c);
input b;
output c;
assign c = b;
module test(input en, output reg y);
always @*
y = en & !y;
endmodule
regression/issue_00067/top_fault.v deleted 100644 → 0
module top(input en, output reg y);
always @*
y = en & !y;
endmodule
regression/issue_00071/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00071/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
reg [31:0] reg_32 = 32'bX;
endmodule
regression/issue_00071/top_fault.v deleted 100644 → 0
module top(b);
input b;
reg [31:0] reg_32 = 32'bX;
endmodule
regression/issue_00078/issue_00078.pat 0 → 100644
\\\X\[0\] , \\\X\[1\] , \\\X\[2\] ,
regression/scripts/issue_00078.ys → regression/issue_00078/issue_00078.ys
read_verilog ../top.v
hierarchy
splitnets -ports
write_verilog synth.v
write_verilog result.out
regression/issue_00078/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00078/top.v
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/issue_00078/top_fault.v deleted 100644 → 0
This source diff could not be displayed because it is too large. You can view the blob instead.
regression/scripts/issue_00781.ys → regression/issue_00081/issue_00081.ys
read_verilog ../top.v
tee -o result.log synth_ice40 -blif test.blif
regression/issue_00081/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00081/top.v
module top(b,c);
input b;
output c;
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
assign c = b;
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
endmodule
module demo_002(y0, y1, y2, y3);
output [63:0] y0, y1, y2, y3;
assign y0 = 1'b_ >= (-1 * -1.17);
assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
assign y3 = 1 ? -1 : 'd0;
endmodule
regression/issue_00081/top_fault.v deleted 100644 → 0
module demo_001(y1, y2, y3, y4);
output [7:0] y1, y2, y3, y4;
localparam [7:0] p1 = 123.45;
localparam real p2 = 123.45;
localparam real p3 = 123;
localparam p4 = 123.45;
assign y1 = p1 + 0.2;
assign y2 = p2 + 0.2;
assign y3 = p3 + 0.2;
assign y4 = p4 + 0.2;
endmodule
module demo_002(y0, y1, y2, y3);
output [63:0] y0, y1, y2, y3;
assign y0 = 1'b_ >= (-1 * -1.17);
assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0;
assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0;
assign y3 = 1 ? -1 : 'd0;
endmodule
regression/issue_00082/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00082/top.v
module top(b);
module a(b);
input b;
reg c;
task a(b);
endmodule
regression/issue_00082/top_fault.v deleted 100644 → 0
module a(b);
input b;
reg c;
task a(b);
endmodule
regression/issue_00083/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00083/top.v
module top(b);
module a(b);
input b;
reg c;parameter
signed b=b;
endmodule
regression/issue_00083/top_fault.v deleted 100644 → 0
module a(b);
input b;
reg c;parameter
signed b=b;
endmodule
regression/issue_00084/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [9:0] addr = 0;
reg ce = 0;
wire [7:0] q;
top uut (
.clk(clk),
.addr(addr),
.ce(ce),
.q(q)
);
always @(posedge clk) begin
addr <= addr + 1;
end
always @(posedge clk) begin
#3;
ce <= !ce;
end
uut_mem_checker q_test(.clk(clk), .en(ce), .A(q));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'b00000000)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00085/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00085/top.v
module top(b,c);
input b;
output c;
assign c = b;
module a;assign a = 0'sh0;
endmodule
regression/issue_00085/top_fault.v deleted 100644 → 0
module a;assign a = 0'sh0;
endmodule
regression/issue_00086/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00086/top.v
module top(b,c);
module top(b);
input b;
output c;
assign c = b;
reg N=0.0/0'H0;
endmodule
regression/issue_00086/top_fault.v deleted 100644 → 0
module top(b);
input b;
reg N=0.0/0'H0;
endmodule
regression/issue_00088/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00089/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00091/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00093/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00095/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00096/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00098/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
always @(clk)
a <= a + 1;
top uut (
.a (a),
.z (z)
);
assert_Z check_output(clk,z[0]);
endmodule
regression/issue_00098/top.v
module top(a,z);
module bug_mika(a,z);
input [7:0] a;
output [7:0] z;
parameter pos = 1;
......
regression/issue_00099/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
wire o1,o2,o3;
always @(clk)
a <= a + 1;
top uut (
.in (a),
.out (z),
.out1 (o1),
.out2 (o2),
.out3 (o3)
);
assert_Z check_output1(clk,o1);
assert_Z check_output2(clk,o2);
assert_Z check_output3(clk,o3);
endmodule
regression/issue_00099/top.v
module top(in, out, out1, out2, out3);
module task_func_test04(in, output, out1, out2, out3);
input [7:0] in;
output [7:0] out;
output [7:0] output;
output out1;
output out2;
output out3;
......
regression/issue_00102/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [35:0] b;
top uut (
.a (clk),
.b (b)
);
assert_Z check_output1(clk,b[0]);
endmodule
regression/issue_00102/top.v
module top (
module test (
a, b
);
input a;
output [35:0] b;
output [1535:0] b;
reg [35:0] G;
reg [1535:0] G;
reg F;
reg H;
reg I;
......@@ -17,8 +17,8 @@ module top (
assign b = muxer(G, {L , H , F , M, J , I}, K, 24, 0);
function [35:0] muxer;
input [35:0] vector;
function [1535:0] muxer;
input [1535:0] vector;
input [23:0] slice;
input [5:0] index;
input size;
......@@ -26,7 +26,7 @@ module top (
input offset;
integer offset;
integer i;
reg [35:0] muxed_value;
reg [1535:0] muxed_value;
begin
muxed_value = vector;
for (i = 0; i < 24; i = i+1)
......
regression/scripts/issue_00111.ys → regression/issue_00111/issue_00111.ys
......@@ -2,7 +2,3 @@ read_verilog ../top.v
synth -top top
splitnets -ports
hierarchy -check
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/issue_00111/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [127:0] state,key = 0;
wire [127:0] out;
/*always @(posedge clk)
begin
state = state + 2300;
key = key + 2500;
end*/
top uut (
.state (state ),
.key (key ),
.out (out )
);
/*genvar index;
generate
for (index=0; index < 128; index=index+25)
begin: gen_code_label
assert_Z check_output(clk,out[index]);
end
endgenerate*/
assert_Z check_output(clk,out[0]);
endmodule
regression/issue_00114/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.clock (clk )
);
endmodule
regression/issue_00114/top.v
module top(
input wire clock
module TestCase(
input wire clock,
);
localparam COUNT = 1600;
......
regression/issue_00126/issue_00126.ys 0 → 100644
read_verilog ../top.v
hierarchy -top test
write_verilog -noexpr -norename result.out
regression/issue_00126/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
always @(posedge clk)
in = in + 1;
top uut (
.in_a(in),
.out_vt(out)
);
endmodule
regression/issue_00126/top.v
module top (in_a, out_vt);
module test (in_a, out_vt);
input [1:0] in_a;
output out_vt;
reg [2:0] result;
assign out_vt = result;
always @(*)
begin
result = 3'b000;
case (in_a)
2'b00 : begin
result = 3'b101;
......@@ -17,8 +21,7 @@ always @(*)
result = 3'b001;
end
default;
default result = 3'b011;
endcase
end
endmodule
regression/issue_00128/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/scripts/issue_00132.ys → regression/issue_00132/issue_00132.ys
read_verilog -defer ../top.v
chparam -set incr 42 topmod
synth -top top
write_verilog synth.v
regression/issue_00132/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00133/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00134/issue_00134.ys 0 → 100644
read_verilog ../top.v
hierarchy -top task_bug
proc; opt; memory; dff2dffe; wreduce; clean; opt
write_verilog -noexpr -norename result.out
regression/issue_00134/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] a = 0;
wire [15:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.in_data (a ),
.do (y )
);
genvar index;
generate
for (index=0; index <= 15; index=index+1)
begin: gen_code_label
assert_X check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00134/top.v
module top ( in_data, do );
module task_bug ( in_data, do );
input [15:0] in_data;
output [15:0] do;
......
regression/issue_00160/issue_00160.ys 0 → 100644
read_verilog ../top.v
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
#equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_LUT4
select -assert-count 2 t:SB_DFFE
select -assert-none t:SB_LUT4 t:SB_DFFE %% t:* %D
regression/issue_00160/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg ce = 1;
wire d;
always @(posedge clk)
begin
a = a + 1;
end
top uut (
.CLKIN(clk),
.A (a ),
.CE (ce),
.D1 (d)
);
assert_X check_output(clk,d);
endmodule
regression/scripts/issue_00171.ys → regression/issue_00171/issue_00171.ys
......@@ -3,5 +3,3 @@ proc; opt; fsm; opt; memory; opt; techmap; opt
scc -all_cell_types
#and then put each found SCC into a module using submod.
scc -all_cell_types
synth -top top
write_verilog synth.v
regression/issue_00171/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 1;
reg ce = 1;
wire [3:0] count;
reg [3:0] count_p;
always @(posedge clk)
begin
rst = 0;
end
always @(posedge clk)
if (rst)
count_p <= 4'd0;
else if (ce)
count_p <= count_p + 4'd1;
top uut (
.clk(clk),
.rst (rst ),
.en (ce),
.count (count)
);
genvar index;
generate
for (index=0; index <= 3; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,count[index],count_p[index]);
end
endgenerate
endmodule
regression/issue_00173/issue_00173.ys 0 → 100644
read_verilog ../top.v
proc
regression/issue_00173/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [2:0] o;
reg [2:0] i;
always @(posedge clk)
i <= i + 1;
top uut (i[0],i[1],i[2],o[0],o[1],o[2]);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],i[index]);
end
endgenerate
endmodule
regression/issue_00174/abc.rc deleted 100644 → 0
# global parameters
set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
set backup # saves backup networks retrived by "undo" and "recall"
set savesteps 1 # sets the maximum number of backup networks to save
set progressbar # display the progress bar
# program names for internal calls
set dotwin dot.exe
set dotunix dot
set gsviewwin gsview32.exe
set gsviewunix gv
set siswin sis.exe
set sisunix sis
set mvsiswin mvsis.exe
set mvsisunix mvsis
set capowin MetaPl-Capo10.1-Win32.exe
set capounix MetaPl-Capo10.1
set gnuplotwin wgnuplot.exe
set gnuplotunix gnuplot
# standard aliases
alias b balance
alias cl cleanup
alias clp collapse
alias esd ext_seq_dcs
alias f fraig
alias fs fraig_sweep
alias fsto fraig_store
alias fres fraig_restore
alias ft fraig_trust
alias lp lutpack
alias pd print_dsd
alias pex print_exdc -d
alias pf print_factor
alias pfan print_fanio
alias pl print_level
alias pio print_io
alias pk print_kmap
alias ps print_stats
alias psu print_supp
alias psy print_symm
alias pun print_unate
alias q quit
alias r read
alias r3 retime -M 3
alias r3f retime -M 3 -f
alias r3b retime -M 3 -b
alias ren renode
alias rh read_hie
alias rl read_blif
alias rb read_bench
alias ret retime
alias rp read_pla
alias rt read_truth
alias rv read_verilog
alias rvl read_verlib
alias rsup read_super mcnc5_old.super
alias rlib read_library
alias rlibc read_library cadence.genlib
alias rw rewrite
alias rwz rewrite -z
alias rf refactor
alias rfz refactor -z
alias re restructure
alias rez restructure -z
alias rs resub
alias rsz resub -z
alias sa set autoexec ps
alias scl scleanup
alias sif if -s
alias so source -x
alias st strash
alias sw sweep
alias ssw ssweep
alias tr0 trace_start
alias tr1 trace_check
alias trt "r c.blif; st; tr0; b; tr1"
alias u undo
alias w write
alias wa write_aiger
alias wb write_bench
alias wc write_cnf
alias wh write_hie
alias wl write_blif
alias wp write_pla
alias wv write_verilog
# standard scripts
alias share "b; ren -s; fx; b"
alias sharedsd "b; ren -b; dsd -g; sw; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias resyn2a "b; rw; b; rw; rwz; b; rwz; b"
alias resyn3 "b; rs; rs -K 6; b; rsz; rsz -K 6; b; rsz -K 5; b"
alias compress "b -l; rw -l; rwz -l; b -l; rwz -l; b -l"
alias compress2 "b -l; rw -l; rf -l; b -l; rw -l; rwz -l; b -l; rfz -l; rwz -l; b -l"
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
alias rwsat "st; rw -l; b -l; rw -l; rf -l"
alias rwsat2 "st; rw -l; b -l; rw -l; rf -l; fraig; rw -l; b -l; rw -l; rf -l"
alias shake "st; ps; sat -C 5000; rw -l; ps; sat -C 5000; b -l; rf -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000; rwz -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000"
# resubstitution scripts for the IWLS paper
alias src_rw "st; rw -l; rwz -l; rwz -l"
alias src_rs "st; rs -K 6 -N 2 -l; rs -K 9 -N 2 -l; rs -K 12 -N 2 -l"
alias src_rws "st; rw -l; rs -K 6 -N 2 -l; rwz -l; rs -K 9 -N 2 -l; rwz -l; rs -K 12 -N 2 -l"
alias resyn2rs "b; rs -K 6; rw; rs -K 6 -N 2; rf; rs -K 8; b; rs -K 8 -N 2; rw; rs -K 10; rwz; rs -K 10 -N 2; b; rs -K 12; rfz; rs -K 12 -N 2; rwz; b"
alias compress2rs "b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; rs -K 8 -N 2 -l; rw -l; rs -K 10 -l; rwz -l; rs -K 10 -N 2 -l; b -l; rs -K 12 -l; rfz -l; rs -K 12 -N 2 -l; rwz -l; b -l"
# experimental implementation of don't-cares
alias resyn2rsdc "b; rs -K 6 -F 2; rw; rs -K 6 -N 2 -F 2; rf; rs -K 8 -F 2; b; rs -K 8 -N 2 -F 2; rw; rs -K 10 -F 2; rwz; rs -K 10 -N 2 -F 2; b; rs -K 12 -F 2; rfz; rs -K 12 -N 2 -F 2; rwz; b"
alias compress2rsdc "b -l; rs -K 6 -F 2 -l; rw -l; rs -K 6 -N 2 -F 2 -l; rf -l; rs -K 8 -F 2 -l; b -l; rs -K 8 -N 2 -F 2 -l; rw -l; rs -K 10 -F 2 -l; rwz -l; rs -K 10 -N 2 -F 2 -l; b -l; rs -K 12 -F 2 -l; rfz -l; rs -K 12 -N 2 -F 2 -l; rwz -l; b -l"
# minimizing for FF literals
alias fflitmin "compress2rs; ren; sop; ps -f"
# temporaries
#alias t "rvl th/lib.v; rvv th/t2.v"
#alias t "so c/pure_sat/test.c"
#alias t "r c/14/csat_998.bench; st; ps"
#alias t0 "r res.blif; aig; mfs"
#alias t "r res2.blif; aig; mfs"
#alias tt "r a/quip_opt/nut_001_opt.blif"
#alias ttb "wh a/quip_opt/nut_001_opt.blif 1.blif"
#alias ttv "wh a/quip_opt/nut_001_opt.blif 1.v"
alias reach "st; ps; compress2; ps; qrel; ps; compress2; ps; qreach -v; ps"
alias qs1 "qvar -I 96 -u; ps; qbf -P 96"
alias qs2 "qvar -I 96 -u; qvar -I 97 -u; ps; qbf -P 96"
alias qs3 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; ps; qbf -P 96"
alias qs4 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; ps; qbf -P 96"
alias qs5 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; ps; qbf -P 96"
alias qs6 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; ps; qbf -P 96"
alias qs7 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; ps; qbf -P 96"
alias qs8 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; ps; qbf -P 96"
alias qs9 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; ps; qbf -P 96"
alias qsA "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; qvar -I 105 -u; ps; qbf -P 96"
alias chnew "st; haig_start; resyn2; haig_use"
alias chnewrs "st; haig_start; resyn2rs; haig_use"
alias stdsd "r test/6in.blif; st; ps; u; bdd; dsd -g; st; ps"
alias trec "rec_start; r c.blif; st; rec_add; rec_use"
alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use"
alias trec5 "rec_start -K 5; r i10.blif; st; rec_add; rec_use"
alias trec6 "rec_start -K 6; r i10.blif; st; rec_add; rec_use"
alias trec7 "rec_start -K 7; r i10.blif; st; rec_add; rec_use"
alias trec8 "rec_start -K 8; r i10.blif; st; rec_add; rec_use"
alias trec10 "rec_start -K 10; r i10.blif; st; rec_add; rec_use"
alias trec12 "rec_start -K 12; r i10.blif; st; rec_add; rec_use"
#alias tsh "r i10_if.blif; st; ps; u; sw; st; ps; cec"
alias tst4 "r i10_if4.blif; st; ps; r x/rec4_.blif; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst4n "r i10_if4.blif; st; ps; r 5npn/all_functions.aig; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst6 "r i10_if6.blif; st; ps; r x/rec6_16_.blif; st; rec_start; r i10_if6.blif; st -r; ps; cec"
#alias t "r c.blif; st; wc c.cnf"
#alias t "r test/dsdmap6.blif; lutpack -vw; cec"
#alias t "r i10_if4.blif; lp"
#alias t1 "r pj1_if4.blif; lp"
#alias t2 "r pj1_if6.blif; lp"
#alias t "r pj/pj1.blif; st; dfraig -v"
#alias t "r c/16/csat_2.bench; st; dfraig -C 100 -v -r"
#alias t "r c/16/csat_147.bench; st; dfraig -C 10 -v -r"
#alias t "r i10.blif; st; ps; csweep; ps; cec"
#alias t "r c/5/csat_777.bench; st; csweep -v"
#alias t "r i10.blif; st; drw -v"
alias t "r c.blif; st; drf"
regression/issue_00174/abc.tcl deleted 100644 → 0
source abc.rc;
print_lut;
resyn;
regression/scripts/issue_00174.ys → regression/issue_00174/issue_00174.ys
......@@ -5,5 +5,3 @@ proc
opt -full
techmap
abc -lut 6
synth -top top
write_verilog synth.v
regression/issue_00174/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [5:0] o;
reg [5:0] i;
wire [5:0] wave_out;
always @(posedge clk)
i <= i + 1;
wire [31:0] w = 1-i;
assign wave_out = w/2;
top uut (i,o);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],wave_out[index]);
end
endgenerate
endmodule
regression/scripts/issue_00175.ys → regression/issue_00175/issue_00175.ys
......@@ -9,5 +9,3 @@ setundef -zero
opt -full -fine
setundef -zero
opt -full -fine
synth -top top
write_verilog synth.v
regression/issue_00655/top.edif deleted 100644 → 0
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regression/issue_00655/top_wo_attrprop.edif deleted 100644 → 0
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