Clean up of tests.

regression/issue_00790/top.v

@@ -7,11 +7,7 @@ module mcve(i_clk, i_value, o_value);
 	always @(posedge i_clk)
 	case(i_value)
 	2'b00: begin end
-`ifndef BUG
 	2'b01: o_value <= 4'h2;
-`else
-	2'b01: o_value <= 4'h3;
-`endif
 	2'b10: o_value <= 4'h4;
 	2'b11: o_value <= 4'h8;
 	default: o_value <= 4'h1;
@@ -21,11 +17,7 @@ module mcve(i_clk, i_value, o_value);
 	case(o_value)
 	4'h0: begin end
 	4'h1: assert(o_value == 4'h1);
-`ifndef BUG
 	4'h2: assert(o_value == 4'h2);
-`else
-	4'h2: assert(o_value == 4'h3);
-`endif
 	4'h4: assert(o_value == 4'h4);
 	4'h8: assert(o_value == 4'h8);
 	default: assert(0);

regression/issue_00922/top.v

@@ -16,11 +16,7 @@ module top
 	// Port A
 	always @ (posedge clka)
 	begin
-`ifndef BUG
 		if (we_a)
-`else
-		if (we_b)
-`endif
 		begin
 			ram[addr_a] <= data_a;
 			q_a <= data_a;
@@ -34,11 +30,7 @@ module top
 	// Port B
 	always @ (posedge clkb)
 	begin
-`ifndef BUG
 		if (we_b)
-`else
-		if (we_a)
-`endif
 		begin
 			ram[addr_b] <= data_b;
 			q_b <= data_b;

regression/issue_00938/top.v

@@ -16,11 +16,7 @@ module top
 	// Port A
 	always @ (posedge clka)
 	begin
-`ifndef BUG
 		if (we_a)
-`else
-		if (we_b)
-`endif
 		begin
 			ram[addr_a] <= data_a;
 			q_a <= data_a;
@@ -34,11 +30,7 @@ module top
 	// Port B
 	always @ (posedge clkb)
 	begin
-`ifndef BUG
 		if (we_b)
-`else
-		if (we_a)
-`endif
 		begin
 			ram[addr_b] <= data_b;
 			q_b <= data_b;

regression/issue_01093/top.v

@@ -10,7 +10,6 @@ module top
  parameter X = 1;
  wire o;
 
-`ifndef BUG
 always @(posedge cin)
 	A <= o;
 
@@ -18,9 +17,6 @@ always @(posedge cin)
 
 middle u_mid (.x(x),.o(o));
 u_rtl inst_u_rtl (.x(x),.o(o));
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule
 

regression/issue_01284/top.v

@@ -8,10 +8,6 @@ module top
  output cout
  );
 
-`ifndef BUG
 assign {cout,A} =  cin + y + x;
-`else
-assign {cout,A} =  cin - y * x;
-`endif
 
 endmodule