Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
Y
yosys-tests
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
yosys-tests
Commits
a965148e
Commit
a965148e
authored
Oct 19, 2019
by
SergeyDegtyar
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Clean up of tests.
parent
7ec04bdd
Hide whitespace changes
Inline
Side-by-side
Showing
5 changed files
with
0 additions
and
32 deletions
+0
-32
regression/issue_00790/top.v
+0
-8
regression/issue_00922/top.v
+0
-8
regression/issue_00938/top.v
+0
-8
regression/issue_01093/top.v
+0
-4
regression/issue_01284/top.v
+0
-4
No files found.
regression/issue_00790/top.v
View file @
a965148e
...
...
@@ -7,11 +7,7 @@ module mcve(i_clk, i_value, o_value);
always
@
(
posedge
i_clk
)
case
(
i_value
)
2'b00
:
begin
end
`ifndef
BUG
2'b01
:
o_value
<=
4'h2
;
`else
2'b01
:
o_value
<=
4'h3
;
`endif
2'b10
:
o_value
<=
4'h4
;
2'b11
:
o_value
<=
4'h8
;
default:
o_value
<=
4'h1
;
...
...
@@ -21,11 +17,7 @@ module mcve(i_clk, i_value, o_value);
case
(
o_value
)
4'h0
:
begin
end
4'h1
:
assert
(
o_value
==
4'h1
)
;
`ifndef
BUG
4'h2
:
assert
(
o_value
==
4'h2
)
;
`else
4'h2
:
assert
(
o_value
==
4'h3
)
;
`endif
4'h4
:
assert
(
o_value
==
4'h4
)
;
4'h8
:
assert
(
o_value
==
4'h8
)
;
default:
assert
(
0
)
;
...
...
regression/issue_00922/top.v
View file @
a965148e
...
...
@@ -16,11 +16,7 @@ module top
// Port A
always
@
(
posedge
clka
)
begin
`ifndef
BUG
if
(
we_a
)
`else
if
(
we_b
)
`endif
begin
ram
[
addr_a
]
<=
data_a
;
q_a
<=
data_a
;
...
...
@@ -34,11 +30,7 @@ module top
// Port B
always
@
(
posedge
clkb
)
begin
`ifndef
BUG
if
(
we_b
)
`else
if
(
we_a
)
`endif
begin
ram
[
addr_b
]
<=
data_b
;
q_b
<=
data_b
;
...
...
regression/issue_00938/top.v
View file @
a965148e
...
...
@@ -16,11 +16,7 @@ module top
// Port A
always
@
(
posedge
clka
)
begin
`ifndef
BUG
if
(
we_a
)
`else
if
(
we_b
)
`endif
begin
ram
[
addr_a
]
<=
data_a
;
q_a
<=
data_a
;
...
...
@@ -34,11 +30,7 @@ module top
// Port B
always
@
(
posedge
clkb
)
begin
`ifndef
BUG
if
(
we_b
)
`else
if
(
we_a
)
`endif
begin
ram
[
addr_b
]
<=
data_b
;
q_b
<=
data_b
;
...
...
regression/issue_01093/top.v
View file @
a965148e
...
...
@@ -10,7 +10,6 @@ module top
parameter
X
=
1
;
wire
o
;
`ifndef
BUG
always
@
(
posedge
cin
)
A
<=
o
;
...
...
@@ -18,9 +17,6 @@ always @(posedge cin)
middle
u_mid
(
.
x
(
x
)
,.
o
(
o
))
;
u_rtl
inst_u_rtl
(
.
x
(
x
)
,.
o
(
o
))
;
`else
assign
{
cout
,
A
}
=
cin
-
y
*
x
;
`endif
endmodule
...
...
regression/issue_01284/top.v
View file @
a965148e
...
...
@@ -8,10 +8,6 @@ module top
output
cout
)
;
`ifndef
BUG
assign
{
cout
,
A
}
=
cin
+
y
+
x
;
`else
assign
{
cout
,
A
}
=
cin
-
y
*
x
;
`endif
endmodule
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment