does not make sense without synth

10d3ec6a · Miodrag Milanovic · 8f9dc1d9 · 8f9dc1d9 · 8f9dc1d9
Commit 10d3ec6a authored Nov 15, 2019 by Miodrag Milanovic
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backends/write_blif/write_blif.ys
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backends/write_blif/write_blif_opt.ys
+0 -6

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--- a/backends/write_blif/write_blif.ys
+++ b/backends/write_blif/write_blif.ys
-read_verilog -sv ../top.v
-proc
-write_blif blif.blif
-design -reset
-read_blif blif.blif
--- a/backends/write_blif/write_blif_opt.ys
+++ b/backends/write_blif/write_blif_opt.ys
-read_verilog -sv ../top.v
-proc
-opt
-write_blif blif.blif
-design -reset
-read_blif blif.blif