Skip to content

Y
yosys-tests
Commit 1098cea6 by SergeyDegtyar
Options

Review and update tests for issues 102-210

parent f67370a3
Showing with 107 additions and 972 deletions
regression/Makefile
......@@ -20,66 +20,6 @@ endef
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00102
$(eval $(call template,issue_00102,issue_00102))
#issue_00111
$(eval $(call template,issue_00111,issue_00111))
#issue_00114
$(eval $(call template,issue_00114,issue_00114))
#issue_00126
$(eval $(call template,issue_00126,issue_00126))
#issue_00128
$(eval $(call template,issue_00128,issue_00128))
#issue_00132
$(eval $(call template,issue_00132,issue_00132))
#issue_00133
$(eval $(call template,issue_00133,issue_00133))
#issue_00134
$(eval $(call template,issue_00134,issue_00134))
#issue_00160
$(eval $(call template,issue_00160,issue_00160))
#issue_00171
$(eval $(call template,issue_00171,issue_00171))
#issue_00173
$(eval $(call template,issue_00173,issue_00173))
#issue_00174
$(eval $(call template,issue_00174,issue_00174))
#issue_00175
$(eval $(call template,issue_00175,issue_00175))
#issue_00182
$(eval $(call template,issue_00182,issue_00182))
#issue_00183
$(eval $(call template,issue_00183,issue_00183))
#issue_00186
$(eval $(call template,issue_00186,issue_00186))
#issue_00194
$(eval $(call template,issue_00194,issue_00194))
#issue_00195
$(eval $(call template,issue_00195,issue_00195))
#issue_00196
$(eval $(call template,issue_00196,issue_00196))
#issue_00210
$(eval $(call template,issue_00210,issue_00210))
#issue_00253
$(eval $(call template,issue_00253,issue_00253))
......
regression/issue_00102/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [35:0] b;
top uut (
.a (clk),
.b (b)
);
assert_Z check_output1(clk,b[0]);
endmodule
regression/issue_00111/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [127:0] state,key = 0;
wire [127:0] out;
/*always @(posedge clk)
begin
state = state + 2300;
key = key + 2500;
end*/
top uut (
.state (state ),
.key (key ),
.out (out )
);
/*genvar index;
generate
for (index=0; index < 128; index=index+25)
begin: gen_code_label
assert_Z check_output(clk,out[index]);
end
endgenerate*/
assert_Z check_output(clk,out[0]);
endmodule
regression/issue_00114/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.clock (clk )
);
endmodule
regression/issue_00126/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] in = 0;
always @(posedge clk)
in = in + 1;
top uut (
.in_a(in),
.out_vt(out)
);
endmodule
regression/issue_00132/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00133/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.a (a ),
.y (y )
);
genvar index;
generate
for (index=0; index <= 7; index=index+1)
begin: gen_code_label
assert_Z check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00134/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [15:0] a = 0;
wire [15:0] y;
always @(posedge clk)
begin
a = a + 3;
end
top uut (
.in_data (a ),
.do (y )
);
genvar index;
generate
for (index=0; index <= 15; index=index+1)
begin: gen_code_label
assert_X check_output(clk,y[index]);
end
endgenerate
endmodule
regression/issue_00160/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg a = 0;
reg ce = 1;
wire d;
always @(posedge clk)
begin
a = a + 1;
end
top uut (
.CLKIN(clk),
.A (a ),
.CE (ce),
.D1 (d)
);
assert_X check_output(clk,d);
endmodule
regression/issue_00171/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg rst = 1;
reg ce = 1;
wire [3:0] count;
reg [3:0] count_p;
always @(posedge clk)
begin
rst = 0;
end
always @(posedge clk)
if (rst)
count_p <= 4'd0;
else if (ce)
count_p <= count_p + 4'd1;
top uut (
.clk(clk),
.rst (rst ),
.en (ce),
.count (count)
);
genvar index;
generate
for (index=0; index <= 3; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,count[index],count_p[index]);
end
endgenerate
endmodule
regression/issue_00173/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [2:0] o;
reg [2:0] i;
always @(posedge clk)
i <= i + 1;
top uut (i[0],i[1],i[2],o[0],o[1],o[2]);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],i[index]);
end
endgenerate
endmodule
regression/issue_00174/abc.rc deleted 100644 → 0
# global parameters
set check # checks intermediate networks
#set checkfio # prints warnings when fanins/fanouts are duplicated
set checkread # checks new networks after reading from file
set backup # saves backup networks retrived by "undo" and "recall"
set savesteps 1 # sets the maximum number of backup networks to save
set progressbar # display the progress bar
# program names for internal calls
set dotwin dot.exe
set dotunix dot
set gsviewwin gsview32.exe
set gsviewunix gv
set siswin sis.exe
set sisunix sis
set mvsiswin mvsis.exe
set mvsisunix mvsis
set capowin MetaPl-Capo10.1-Win32.exe
set capounix MetaPl-Capo10.1
set gnuplotwin wgnuplot.exe
set gnuplotunix gnuplot
# standard aliases
alias b balance
alias cl cleanup
alias clp collapse
alias esd ext_seq_dcs
alias f fraig
alias fs fraig_sweep
alias fsto fraig_store
alias fres fraig_restore
alias ft fraig_trust
alias lp lutpack
alias pd print_dsd
alias pex print_exdc -d
alias pf print_factor
alias pfan print_fanio
alias pl print_level
alias pio print_io
alias pk print_kmap
alias ps print_stats
alias psu print_supp
alias psy print_symm
alias pun print_unate
alias q quit
alias r read
alias r3 retime -M 3
alias r3f retime -M 3 -f
alias r3b retime -M 3 -b
alias ren renode
alias rh read_hie
alias rl read_blif
alias rb read_bench
alias ret retime
alias rp read_pla
alias rt read_truth
alias rv read_verilog
alias rvl read_verlib
alias rsup read_super mcnc5_old.super
alias rlib read_library
alias rlibc read_library cadence.genlib
alias rw rewrite
alias rwz rewrite -z
alias rf refactor
alias rfz refactor -z
alias re restructure
alias rez restructure -z
alias rs resub
alias rsz resub -z
alias sa set autoexec ps
alias scl scleanup
alias sif if -s
alias so source -x
alias st strash
alias sw sweep
alias ssw ssweep
alias tr0 trace_start
alias tr1 trace_check
alias trt "r c.blif; st; tr0; b; tr1"
alias u undo
alias w write
alias wa write_aiger
alias wb write_bench
alias wc write_cnf
alias wh write_hie
alias wl write_blif
alias wp write_pla
alias wv write_verilog
# standard scripts
alias share "b; ren -s; fx; b"
alias sharedsd "b; ren -b; dsd -g; sw; fx; b"
alias resyn "b; rw; rwz; b; rwz; b"
alias resyn2 "b; rw; rf; b; rw; rwz; b; rfz; rwz; b"
alias resyn2a "b; rw; b; rw; rwz; b; rwz; b"
alias resyn3 "b; rs; rs -K 6; b; rsz; rsz -K 6; b; rsz -K 5; b"
alias compress "b -l; rw -l; rwz -l; b -l; rwz -l; b -l"
alias compress2 "b -l; rw -l; rf -l; b -l; rw -l; rwz -l; b -l; rfz -l; rwz -l; b -l"
alias choice "fraig_store; resyn; fraig_store; resyn2; fraig_store; fraig_restore"
alias choice2 "fraig_store; balance; fraig_store; resyn; fraig_store; resyn2; fraig_store; resyn2; fraig_store; fraig_restore"
alias rwsat "st; rw -l; b -l; rw -l; rf -l"
alias rwsat2 "st; rw -l; b -l; rw -l; rf -l; fraig; rw -l; b -l; rw -l; rf -l"
alias shake "st; ps; sat -C 5000; rw -l; ps; sat -C 5000; b -l; rf -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000; rwz -l; ps; sat -C 5000; rfz -l; ps; sat -C 5000"
# resubstitution scripts for the IWLS paper
alias src_rw "st; rw -l; rwz -l; rwz -l"
alias src_rs "st; rs -K 6 -N 2 -l; rs -K 9 -N 2 -l; rs -K 12 -N 2 -l"
alias src_rws "st; rw -l; rs -K 6 -N 2 -l; rwz -l; rs -K 9 -N 2 -l; rwz -l; rs -K 12 -N 2 -l"
alias resyn2rs "b; rs -K 6; rw; rs -K 6 -N 2; rf; rs -K 8; b; rs -K 8 -N 2; rw; rs -K 10; rwz; rs -K 10 -N 2; b; rs -K 12; rfz; rs -K 12 -N 2; rwz; b"
alias compress2rs "b -l; rs -K 6 -l; rw -l; rs -K 6 -N 2 -l; rf -l; rs -K 8 -l; b -l; rs -K 8 -N 2 -l; rw -l; rs -K 10 -l; rwz -l; rs -K 10 -N 2 -l; b -l; rs -K 12 -l; rfz -l; rs -K 12 -N 2 -l; rwz -l; b -l"
# experimental implementation of don't-cares
alias resyn2rsdc "b; rs -K 6 -F 2; rw; rs -K 6 -N 2 -F 2; rf; rs -K 8 -F 2; b; rs -K 8 -N 2 -F 2; rw; rs -K 10 -F 2; rwz; rs -K 10 -N 2 -F 2; b; rs -K 12 -F 2; rfz; rs -K 12 -N 2 -F 2; rwz; b"
alias compress2rsdc "b -l; rs -K 6 -F 2 -l; rw -l; rs -K 6 -N 2 -F 2 -l; rf -l; rs -K 8 -F 2 -l; b -l; rs -K 8 -N 2 -F 2 -l; rw -l; rs -K 10 -F 2 -l; rwz -l; rs -K 10 -N 2 -F 2 -l; b -l; rs -K 12 -F 2 -l; rfz -l; rs -K 12 -N 2 -F 2 -l; rwz -l; b -l"
# minimizing for FF literals
alias fflitmin "compress2rs; ren; sop; ps -f"
# temporaries
#alias t "rvl th/lib.v; rvv th/t2.v"
#alias t "so c/pure_sat/test.c"
#alias t "r c/14/csat_998.bench; st; ps"
#alias t0 "r res.blif; aig; mfs"
#alias t "r res2.blif; aig; mfs"
#alias tt "r a/quip_opt/nut_001_opt.blif"
#alias ttb "wh a/quip_opt/nut_001_opt.blif 1.blif"
#alias ttv "wh a/quip_opt/nut_001_opt.blif 1.v"
alias reach "st; ps; compress2; ps; qrel; ps; compress2; ps; qreach -v; ps"
alias qs1 "qvar -I 96 -u; ps; qbf -P 96"
alias qs2 "qvar -I 96 -u; qvar -I 97 -u; ps; qbf -P 96"
alias qs3 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; ps; qbf -P 96"
alias qs4 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; ps; qbf -P 96"
alias qs5 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; ps; qbf -P 96"
alias qs6 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; ps; qbf -P 96"
alias qs7 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; ps; qbf -P 96"
alias qs8 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; ps; qbf -P 96"
alias qs9 "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; ps; qbf -P 96"
alias qsA "qvar -I 96 -u; qvar -I 97 -u; qvar -I 98 -u; qvar -I 99 -u; qvar -I 100 -u; qvar -I 101 -u; qvar -I 102 -u; qvar -I 103 -u; qvar -I 104 -u; qvar -I 105 -u; ps; qbf -P 96"
alias chnew "st; haig_start; resyn2; haig_use"
alias chnewrs "st; haig_start; resyn2rs; haig_use"
alias stdsd "r test/6in.blif; st; ps; u; bdd; dsd -g; st; ps"
alias trec "rec_start; r c.blif; st; rec_add; rec_use"
alias trec4 "rec_start -K 4; r i10.blif; st; rec_add; rec_use"
alias trec5 "rec_start -K 5; r i10.blif; st; rec_add; rec_use"
alias trec6 "rec_start -K 6; r i10.blif; st; rec_add; rec_use"
alias trec7 "rec_start -K 7; r i10.blif; st; rec_add; rec_use"
alias trec8 "rec_start -K 8; r i10.blif; st; rec_add; rec_use"
alias trec10 "rec_start -K 10; r i10.blif; st; rec_add; rec_use"
alias trec12 "rec_start -K 12; r i10.blif; st; rec_add; rec_use"
#alias tsh "r i10_if.blif; st; ps; u; sw; st; ps; cec"
alias tst4 "r i10_if4.blif; st; ps; r x/rec4_.blif; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst4n "r i10_if4.blif; st; ps; r 5npn/all_functions.aig; st; rec_start; r i10_if4.blif; st -r; ps; cec"
alias tst6 "r i10_if6.blif; st; ps; r x/rec6_16_.blif; st; rec_start; r i10_if6.blif; st -r; ps; cec"
#alias t "r c.blif; st; wc c.cnf"
#alias t "r test/dsdmap6.blif; lutpack -vw; cec"
#alias t "r i10_if4.blif; lp"
#alias t1 "r pj1_if4.blif; lp"
#alias t2 "r pj1_if6.blif; lp"
#alias t "r pj/pj1.blif; st; dfraig -v"
#alias t "r c/16/csat_2.bench; st; dfraig -C 100 -v -r"
#alias t "r c/16/csat_147.bench; st; dfraig -C 10 -v -r"
#alias t "r i10.blif; st; ps; csweep; ps; cec"
#alias t "r c/5/csat_777.bench; st; csweep -v"
#alias t "r i10.blif; st; drw -v"
alias t "r c.blif; st; drf"
regression/issue_00174/abc.tcl deleted 100644 → 0
source abc.rc;
print_lut;
resyn;
regression/issue_00174/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [5:0] o;
reg [5:0] i;
wire [5:0] wave_out;
always @(posedge clk)
i <= i + 1;
wire [31:0] w = 1-i;
assign wave_out = w/2;
top uut (i,o);
genvar index;
generate
for (index=0; index <= 2; index=index+1)
begin: gen_code_label
assert_dff check_output(clk,o[index],wave_out[index]);
end
endgenerate
endmodule
regression/issue_00175/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire GC;
wire GC_p;
reg E = 0;
always @(posedge clk)
E = ~E;
reg ED;
always@(*) begin
if(~clk)
ED = E;
end
assign GC_p = clk & ED;
top uut (clk,CG,E);
assert_dff check_output(clk,GC,GC_p);
endmodule
regression/issue_00182/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
endmodule
regression/issue_00183/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire out;
top uut (clk,out);
assert_dff check_output (clk,out,1'b1);
endmodule
regression/issue_00186/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] adr = 0;
reg [1:0] din = 0;
wire [1:0] q;
reg mem_init = 0;
always @(posedge clk) begin
#3;
din <= din + 1;
adr <= adr + 1;
end
always @(posedge adr) begin
#10;
if(adr == 2'b11)
mem_init <= 1;
end
top uut (adr,clk,din,q);
uut_mem_checker port_b_test(.clk(clk), .init(mem_init), .A(q));
endmodule
module uut_mem_checker(input clk, input init, input [1:0] A);
always @(posedge clk)
begin
#1;
if (init == 1 & A === 2'bXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00194/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
//$dumpfile("testbench.vcd");
//$dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire out;
top uut (clk,out);
assert_dff check_output (clk,out,1'b1);
endmodule
regression/issue_00195/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00196/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire a,b,c,d,e,f;
top uut(clk,a,b,c,d,e,f);
endmodule
regression/issue_00210/testbench.v deleted 100644 → 0
`timescale 1ns/1ps
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire [9:0] a;
top uut(a);
endmodule
regression/scripts/issue_00018.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
select -assert-any w:*i
write_verilog synth.v
regression/scripts/issue_00059.ys deleted 100644 → 0
read_verilog ../top.v
#Myname: added some comment with a colon
synth -top top
write_verilog synth.v
regression/scripts/issue_00067.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00071.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00078.ys deleted 100644 → 0
read_verilog ../top.v
hierarchy
splitnets -ports
write_verilog synth.v
regression/scripts/issue_00081.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00082.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00083.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00084.ys deleted 100644 → 0
read_verilog ../top.v
synth_xilinx -top top
cd top
select -assert-count 1 t:RAMB18E1
\ No newline at end of file
regression/scripts/issue_00085.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00086.ys deleted 100644 → 0
read_verilog ../top_fault.v
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00095.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00096.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00098.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00099.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00102.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00114.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00126.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00128.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00133.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00160.ys deleted 100644 → 0
read_verilog ../top.v
synth_ice40 -top top
write_verilog synth.v
regression/scripts/issue_00173.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00195.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/scripts/issue_00210.ys deleted 100644 → 0
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression_revised/Makefile
......@@ -90,4 +90,64 @@ $(eval $(call template,issue_00098,issue_00098))
#issue_00099
$(eval $(call template,issue_00099,issue_00099_fail))
#issue_00102
$(eval $(call template,issue_00102,issue_00102))
#issue_00111
$(eval $(call template,issue_00111,issue_00111))
#issue_00114
$(eval $(call template,issue_00114,issue_00114))
#issue_00126
$(eval $(call template,issue_00126,issue_00126))
#issue_00128
$(eval $(call template,issue_00128,issue_00128))
#issue_00132
$(eval $(call template,issue_00132,issue_00132))
#issue_00133
$(eval $(call template,issue_00133,issue_00133))
#issue_00134
$(eval $(call template,issue_00134,issue_00134))
#issue_00160
$(eval $(call template,issue_00160,issue_00160))
#issue_00171
$(eval $(call template,issue_00171,issue_00171))
#issue_00173
$(eval $(call template,issue_00173,issue_00173))
#issue_00174
$(eval $(call template,issue_00174,issue_00174))
#issue_00175
$(eval $(call template,issue_00175,issue_00175))
#issue_00182
$(eval $(call template,issue_00182,issue_00182))
#issue_00183
$(eval $(call template,issue_00183,issue_00183))
#issue_00186
$(eval $(call template,issue_00186,issue_00186))
#issue_00194
$(eval $(call template,issue_00194,issue_00194))
#issue_00195
$(eval $(call template,issue_00195,issue_00195))
#issue_00196
$(eval $(call template,issue_00196,issue_00196_fail))
#issue_00210
$(eval $(call template,issue_00210,issue_00210))
.PHONY: all clean
regression/issue_00102/top.v → regression_revised/issue_00102/top.v
module top (
module test (
a, b
);
input a;
output [35:0] b;
output [1535:0] b;
reg [35:0] G;
reg [1535:0] G;
reg F;
reg H;
reg I;
......@@ -17,8 +17,8 @@ module top (
assign b = muxer(G, {L , H , F , M, J , I}, K, 24, 0);
function [35:0] muxer;
input [35:0] vector;
function [1535:0] muxer;
input [1535:0] vector;
input [23:0] slice;
input [5:0] index;
input size;
......@@ -26,7 +26,7 @@ module top (
input offset;
integer offset;
integer i;
reg [35:0] muxed_value;
reg [1535:0] muxed_value;
begin
muxed_value = vector;
for (i = 0; i < 24; i = i+1)
......
regression/scripts/issue_00111.ys → regression_revised/issue_00111/issue_00111.ys
......@@ -2,7 +2,3 @@ read_verilog ../top.v
synth -top top
splitnets -ports
hierarchy -check
design -reset
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression/issue_00114/top.v → regression_revised/issue_00114/top.v
module top(
input wire clock
module TestCase(
input wire clock,
);
localparam COUNT = 1600;
......
regression_revised/issue_00126/issue_00126.ys 0 → 100644
read_verilog ../top.v
hierarchy -top test
write_verilog -noexpr -norename result.out
regression/issue_00126/top.v → regression_revised/issue_00126/top.v
module top (in_a, out_vt);
module test (in_a, out_vt);
input [1:0] in_a;
output out_vt;
reg [2:0] result;
assign out_vt = result;
always @(*)
begin
result = 3'b000;
case (in_a)
2'b00 : begin
result = 3'b101;
......@@ -17,8 +21,7 @@ always @(*)
result = 3'b001;
end
default;
default result = 3'b011;
endcase
end
endmodule
regression/scripts/issue_00132.ys → regression_revised/issue_00132/issue_00132.ys
read_verilog -defer ../top.v
chparam -set incr 42 topmod
synth -top top
write_verilog synth.v
regression/scripts/issue_00134.ys → regression_revised/issue_00134/issue_00134.ys
read_verilog ../top.v
hierarchy -top top
hierarchy -top task_bug
proc; opt; memory; dff2dffe; wreduce; clean; opt
write_verilog -noexpr -norename synth.v
write_verilog -noexpr -norename result.out
regression/issue_00134/top.v → regression_revised/issue_00134/top.v
module top ( in_data, do );
module task_bug ( in_data, do );
input [15:0] in_data;
output [15:0] do;
......
regression_revised/issue_00160/issue_00160.ys 0 → 100644
read_verilog ../top.v
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
#equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_LUT4
select -assert-count 2 t:SB_DFFE
select -assert-none t:SB_LUT4 t:SB_DFFE %% t:* %D
regression/scripts/issue_00171.ys → regression_revised/issue_00171/issue_00171.ys
......@@ -3,5 +3,3 @@ proc; opt; fsm; opt; memory; opt; techmap; opt
scc -all_cell_types
#and then put each found SCC into a module using submod.
scc -all_cell_types
synth -top top
write_verilog synth.v
regression/scripts/issue_00174.ys → regression_revised/issue_00174/issue_00174.ys
......@@ -5,5 +5,3 @@ proc
opt -full
techmap
abc -lut 6
synth -top top
write_verilog synth.v
regression/scripts/issue_00175.ys → regression_revised/issue_00175/issue_00175.ys
......@@ -9,5 +9,3 @@ setundef -zero
opt -full -fine
setundef -zero
opt -full -fine
synth -top top
write_verilog synth.v
regression/scripts/issue_00182.ys → regression_revised/issue_00182/issue_00182.ys
read_verilog ../top.v
synth_ice40 -blif litescope.bli -top top
write_verilog synth.v
regression/scripts/issue_00183.ys → regression_revised/issue_00183/issue_00183.ys
read_verilog ../top.v
synth_ice40 -top top -blif test.blif
write_verilog synth.v
regression_revised/issue_00186/issue_00186.pat 0 → 100644
assign _07_\[0\] = adr\[0\] ? \\ram\[3\] \[0\] : \\ram\[2\] \[0\];
assign _07_\[1\] = adr\[0\] ? \\ram\[3\] \[1\] : \\ram\[2\] \[1\];
regression/scripts/issue_00186.ys → regression_revised/issue_00186/issue_00186.ys
read_verilog -DTEST_1 ../top.v
hierarchy -top top
proc
memory
proc; memory
opt -full
techmap
write_verilog -noattr synth.v
write_verilog -noattr result.out
regression_revised/issue_00196/issue_00196_fail.pat 0 → 100644
ERROR: Found posedge/negedge event on a signal that is not 1 bit wide!
regression/scripts/issue_00196.ys → regression_revised/issue_00196/issue_00196_fail.ys
read_verilog ../top.v
synth_greenpak4 -json 3pdrive.json
write_verilog synth.v
regression_revised/run.sh
......@@ -36,13 +36,20 @@ else
exit 0
else
#3 Output log check
if [ -f "../$2.pat" ]; then
if [ -f "../$2.pat" ]; then # Expected behavior
expectation=$(<../$2.pat)
if grep "$expectation" result.out; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
elif [ -f "../$2_n.pat" ]; then # Not expected behavior
expectation=$(<../$2_n.pat)
if grep "$expectation" result.out; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
#1 Iverilog run when testbench exists
elif [ -f "../testbench.v" ]; then
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment