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yosys-tests
Commit f67370a3 by SergeyDegtyar
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The third variant of changes in yosys-tests

parent 2c633693
Showing with 403 additions and 756 deletions
Makefile
SUBDIRS := architecture backends bigsim equiv frontends misc regression simple yosys
SUBDIRS := architecture backends bigsim equiv frontends misc regression regression_revised simple yosys
ifeq ($(VERIFIC),1)
export VERIFIC=1
......
regression/Makefile
......@@ -20,81 +20,6 @@ endef
#issue_00790
$(eval $(call template,issue_00790,issue_00790))
#issue_00018
$(eval $(call template,issue_00018,issue_00018))
#issue_00041
$(eval $(call template,issue_00041,issue_00041))
#issue_00059
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
ifeq ($(ENABLE_HEAVY_TESTS),1)
$(eval $(call template,issue_00065,issue_00065))
endif
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
#issue_00071
$(eval $(call template,issue_00071,issue_00071))
#issue_00078
$(eval $(call template,issue_00078,issue_00078))
#issue_00081
$(eval $(call template,issue_00081,issue_00081))
#issue_00082
#yosys> read_verilog top_fault.v
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top_fault.v' to AST representation.
#top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
#
$(eval $(call template,issue_00082,issue_00082))
#issue_00083
#Warning: Deep recursion in AST simplifier.
#Does this design contain insanely long expressions?
#run.sh: line 21: 17264 Segmentation fault (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
#make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
#
$(eval $(call template,issue_00083,issue_00083))
#issue_00084
$(eval $(call template,issue_00084,issue_00084))
#issue_00085
$(eval $(call template,issue_00085,issue_00085))
#issue_00086
$(eval $(call template,issue_00086,issue_00086))
#issue_00088
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
$(eval $(call template,issue_00089,issue_00089))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
$(eval $(call template,issue_00093,issue_00093))
#issue_00095
$(eval $(call template,issue_00095,issue_00095))
#issue_00096
$(eval $(call template,issue_00096,issue_00096))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
#issue_00099
$(eval $(call template,issue_00099,issue_00099))
#issue_00102
$(eval $(call template,issue_00102,issue_00102))
......
regression/issue_00018/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [1:0] a = 0;
reg rst = 0;
top uut (
.x(x),
.clk(clk),
.rst(rst),
.a(a)
);
always @(posedge clk) begin
a <= a + 1;
end
always @(posedge clk) begin
#2;
rst <= !rst;
end
uut_checker q_test(.clk(clk), .en(rst), .A(x));
endmodule
module uut_checker(input clk, input en, input A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 1'bz)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00018/top.v deleted 100644 → 0
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module top (
x,clk,rst,a
);
output x;
reg x;
input clk;
input rst;
input [1:0] a;
always @(posedge clk, negedge rst) begin: DESIGN_PROCESSOR
reg i;
if (!rst) begin
i = 0;
x = 0;
end
else begin
case (a)
2'b00: begin
x = 0;
i = 0;
end
2'b01: begin
x = i;
end
2'b10: begin
i = 1;
end
2'b11: begin
i = 0;
end
default: begin
x = 0;
i = 0;
end
endcase
end
end
endmodule
regression/issue_00041/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00059/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00065/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] in = 0;
wire [7:0] out;
always @(posedge clk) begin
in <= in + 1;
end
top uut (
.alu_data_d_in (in ),
.alu_data_d_out (out )
);
uut_checker q_test(.clk(clk), .A(out));
endmodule
module uut_checker(input clk, input [7:0] A);
always @(posedge clk)
begin
#1;
if (A === 8'bXXXXXXXX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00067/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00067/top.v deleted 100644 → 0
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00071/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00071/top.v deleted 100644 → 0
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00078/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00078/top.v deleted 100644 → 0
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00081/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00081/top.v deleted 100644 → 0
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00082/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00082/top.v deleted 100644 → 0
module top(b);
input b;
endmodule
regression/issue_00083/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00083/top.v deleted 100644 → 0
module top(b);
input b;
endmodule
regression/issue_00084/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
#5 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [9:0] addr = 0;
reg ce = 0;
wire [7:0] q;
top uut (
.clk(clk),
.addr(addr),
.ce(ce),
.q(q)
);
always @(posedge clk) begin
addr <= addr + 1;
end
always @(posedge clk) begin
#3;
ce <= !ce;
end
uut_mem_checker q_test(.clk(clk), .en(ce), .A(q));
endmodule
module uut_mem_checker(input clk, input en, input [7:0] A);
always @(posedge clk)
begin
#1;
if (en == 1 & A === 8'b00000000)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
regression/issue_00085/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00085/top.v deleted 100644 → 0
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00086/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00086/top.v deleted 100644 → 0
module top(b,c);
input b;
output c;
assign c = b;
endmodule
regression/issue_00088/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire c;
top uut (
.b (clk ),
.c (c)
);
endmodule
regression/issue_00089/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00091/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
wire rst = 0;
wire A;
top uut (
.A (A),
.clk (clk),
.rst (rst)
);
endmodule
regression/issue_00093/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00095/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00096/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
top uut (
.b (clk )
);
endmodule
regression/issue_00098/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
always @(clk)
a <= a + 1;
top uut (
.a (a),
.z (z)
);
assert_Z check_output(clk,z[0]);
endmodule
regression/issue_00099/testbench.v deleted 100644 → 0
module testbench;
reg clk;
initial begin
// $dumpfile("testbench.vcd");
// $dumpvars(0, testbench);
#0 clk = 0;
repeat (10000) begin
#5 clk = 1;
#5 clk = 0;
end
$display("OKAY");
end
reg [7:0] a = 0;
wire [7:0] z;
wire o1,o2,o3;
always @(clk)
a <= a + 1;
top uut (
.in (a),
.out (z),
.out1 (o1),
.out2 (o2),
.out3 (o3)
);
assert_Z check_output1(clk,o1);
assert_Z check_output2(clk,o2);
assert_Z check_output3(clk,o3);
endmodule
regression_revised/Makefile 0 → 100644
all: work
touch .stamp
clean::
rm -f .stamp
define template
$(foreach design,$(1),
$(foreach script,$(2),
work:: $(design)/work_$(script)/.stamp
$(design)/work_$(script)/.stamp:
./run.sh $(design) $(script)
clean::
rm -rf $(design)/work_$(script)
))
endef
#issue_00018
$(eval $(call template,issue_00018,issue_00018))
#issue_00041
$(eval $(call template,issue_00041,issue_00041))
#issue_00059
$(eval $(call template,issue_00059,issue_00059))
#issue_00065
$(eval $(call template,issue_00065,issue_00065))
#issue_00067
$(eval $(call template,issue_00067,issue_00067))
#issue_00071
$(eval $(call template,issue_00071,issue_00071))
#issue_00078
$(eval $(call template,issue_00078,issue_00078))
#issue_00081
$(eval $(call template,issue_00081,issue_00081))
#issue_00082
#yosys> read_verilog top_fault.v
#1. Executing Verilog-2005 frontend.
#Parsing Verilog input from `top_fault.v' to AST representation.
#top_fault.v:4: ERROR: Internal error - should not happen - no AST_WIRE node.
#
$(eval $(call template,issue_00082,issue_00082_fail))
#issue_00083
#Warning: Deep recursion in AST simplifier.
#Does this design contain insanely long expressions?
#run.sh: line 21: 17264 Segmentation fault (core dumped) yosys -ql yosys.log ../../scripts/$2.ys
#make: *** [Makefile:24: issue_00083/work_issue_00083/.stamp] Error 139
#
$(eval $(call template,issue_00083,issue_00083_fail))
#issue_00084
$(eval $(call template,issue_00084,issue_00084))
#issue_00085
$(eval $(call template,issue_00085,issue_00085))
#issue_00086
$(eval $(call template,issue_00086,issue_00086))
#issue_00088
$(eval $(call template,issue_00088,issue_00088))
#issue_00089
$(eval $(call template,issue_00089,issue_00089_fail))
#issue_00091
$(eval $(call template,issue_00091,issue_00091))
#issue_00093
$(eval $(call template,issue_00093,issue_00093_fail))
#issue_00095
$(eval $(call template,issue_00095,issue_00095_fail))
#issue_00096
$(eval $(call template,issue_00096,issue_00096_fail))
#issue_00098
$(eval $(call template,issue_00098,issue_00098))
#issue_00099
$(eval $(call template,issue_00099,issue_00099_fail))
.PHONY: all clean
regression_revised/common.v 0 → 100644
module assert_dff(input clk, input test, input pat);
always @(posedge clk)
begin
#2
if (test != pat)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time);
$stop;
end
end
endmodule
module assert_tri(input en, input A, input B);
always @(posedge en)
begin
//#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
module assert_Z(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bZ)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_X(input clk, input A);
always @(posedge clk)
begin
//#1;
if (A === 1'bX)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A);
$stop;
end
end
endmodule
module assert_comb(input A, input B);
always @(*)
begin
#1;
if (A !== B)
begin
$display("ERROR: ASSERTION FAILED in %m:",$time," ",A," ",B);
$stop;
end
end
endmodule
regression_revised/issue_00018/issue_00018.ys 0 → 100644
read_verilog ../top.v
synth -top d
regression_revised/issue_00018/top.v 0 → 100644
// File: design.v
// Generated by MyHDL 0.8
// Date: Tue Dec 3 04:33:14 2013
`timescale 1ns/10ps
module d (
cos_z0,
sin_z0,
done,
z0,
start,
clock,
reset
);
// Sine and cosine computer.
//
// This module computes the sine and cosine of an input angle. The
// floating point numbers are represented as integers by scaling them
// up with a factor corresponding to the number of bits after the point.
//
// Ports:
// -----
// cos_z0: cosine of the input angle
// sin_z0: sine of the input angle
// done: output flag indicated completion of the computation
// z0: input angle
// start: input that starts the computation on a posedge
// clock: clock input
// reset: reset input
output signed [19:0] cos_z0;
reg signed [19:0] cos_z0;
output signed [19:0] sin_z0;
reg signed [19:0] sin_z0;
output done;
reg done;
input signed [19:0] z0;
input start;
input clock;
input reset;
always @(posedge clock, posedge reset) begin: DESIGN_PROCESSOR
reg [5-1:0] i;
reg [1-1:0] state;
reg signed [20-1:0] dz;
reg signed [20-1:0] dx;
reg signed [20-1:0] dy;
reg signed [20-1:0] y;
reg signed [20-1:0] x;
reg signed [20-1:0] z;
if (reset) begin
state = 1'b0;
cos_z0 <= 1;
sin_z0 <= 0;
done <= 1'b0;
x = 0;
y = 0;
z = 0;
i = 0;
end
else begin
case (state)
1'b0: begin
if (start) begin
x = 159188;
y = 0;
z = z0;
i = 0;
done <= 1'b0;
state = 1'b1;
end
end
1'b1: begin
dx = $signed(y >>> $signed({1'b0, i}));
dy = $signed(x >>> $signed({1'b0, i}));
case (i)
0: dz = 205887;
1: dz = 121542;
2: dz = 64220;
3: dz = 32599;
4: dz = 16363;
5: dz = 8189;
6: dz = 4096;
7: dz = 2048;
8: dz = 1024;
9: dz = 512;
10: dz = 256;
11: dz = 128;
12: dz = 64;
13: dz = 32;
14: dz = 16;
15: dz = 8;
16: dz = 4;
17: dz = 2;
default: dz = 1;
endcase
if ((z >= 0)) begin
x = x - dx;
y = y + dy;
z = z - dz;
end
else begin
x = x + dx;
y = y - dy;
z = z + dz;
end
if ((i == (19 - 1))) begin
cos_z0 <= x;
sin_z0 <= y;
state = 1'b0;
done <= 1'b1;
end
else begin
i = i + 1;
end
end
endcase
end
end
endmodule
regression_revised/issue_00041/issue_00041.ys 0 → 100644
read_verilog ../top.v
synth -top top
write_verilog synth.v
regression_revised/issue_00059/issue_00059.ys 0 → 100644
read_verilog ../top.v
#Myname: added some comment with a colon
synth -top top
regression_revised/issue_00065/issue_00065.ys 0 → 100644
read_verilog ../top.v
synth -top top
regression/issue_00067/top_fault.v → regression_revised/issue_00067/top.v
module top(input en, output reg y);
module test(input en, output reg y);
always @*
y = en & !y;
endmodule
regression_revised/issue_00078/issue_00078.pat 0 → 100644
\\\X\[0\] , \\\X\[1\] , \\\X\[2\] ,
regression_revised/issue_00078/issue_00078.ys 0 → 100644
read_verilog ../top.v
hierarchy
splitnets -ports
write_verilog result.out
regression_revised/issue_00084/issue_00084.ys 0 → 100644
read_verilog ../top.v
synth_xilinx -top top
cd top
select -assert-count 1 t:RAMB18E1
\ No newline at end of file
regression_revised/issue_00093/issue_00093_fail.ys 0 → 100644
read_verilog ../top.v
synth -top top
regression_revised/issue_00095/issue_00095_fail.ys 0 → 100644
read_verilog ../top.v
synth -top top
regression_revised/issue_00096/issue_00096_fail.ys 0 → 100644
read_verilog ../top.v
synth -top top
regression/issue_00098/top.v → regression_revised/issue_00098/top.v
module top(a,z);
module bug_mika(a,z);
input [7:0] a;
output [7:0] z;
parameter pos = 1;
......
regression/issue_00099/top.v → regression_revised/issue_00099/top.v
module top(in, out, out1, out2, out3);
module task_func_test04(in, output, out1, out2, out3);
input [7:0] in;
output [7:0] out;
output [7:0] output;
output out1;
output out2;
output out3;
......
regression_revised/run.sh 0 → 100755
#!/bin/bash
set -x
test -d $1
test -f $2.ys
rm -rf $1/work_$2
mkdir $1/work_$2
cd $1/work_$2
touch .start
#
if [[ $2 =~ "_fail" ]]; then
#4 - An error expected
if yosys -ql yosys.log ../$2.ys; then
echo FAIL > ${1}_${2}.status
else
if [ -f "../$2.pat" ]; then
expectation=$(<../$2.pat)
if grep "$expectation" yosys.log; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
else
echo PASS > ${1}_${2}.status
fi
fi
else
#2 - All asserts in .ys script
yosys -ql yosys.log ../$2.ys
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
else
#3 Output log check
if [ -f "../$2.pat" ]; then
expectation=$(<../$2.pat)
if grep "$expectation" result.out; then
echo PASS > ${1}_${2}.status
else
echo FAIL > ${1}_${2}.status
fi
#1 Iverilog run when testbench exists
elif [ -f "../testbench.v" ]; then
if [ -f "../../../../../techlibs/common/simcells.v" ]; then
COMMON_PREFIX=../../../../../techlibs/common
TECHLIBS_PREFIX=../../../../../techlibs
else
COMMON_PREFIX=/usr/local/share/yosys
TECHLIBS_PREFIX=/usr/local/share/yosys
fi
if [ -f "../iverilog_adds.txt" ]; then
iverilog_adds=$(<../iverilog_adds.txt)
else
iverilog_adds=""
fi
iverilog -o testbench ../testbench.v synth.v ../../common.v $COMMON_PREFIX/simcells.v $COMMON_PREFIX/simlib.v $iverilog_adds
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
touch .stamp
exit 0
fi
if ! vvp -N testbench > testbench.log 2>&1; then
grep 'ERROR' testbench.log
echo FAIL > ${1}_${2}.status
elif grep 'ERROR' testbench.log || ! grep 'OKAY' testbench.log; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
else
echo PASS > ${1}_${2}.status
fi
fi
fi
touch .stamp
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