More renaming

architecture/synth_xilinx_srl/test9.v → architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_N_width.v

 // Check multi-bit works
 // neg_clk_no_enable_with_init_with_inferred_N_width
 (* top *)
-module test9 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
+module neg_clk_no_enable_with_init_with_inferred_N_width #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
 
@@ -24,6 +24,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test9; select t:FD* -assert-none";
+    wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_N_width; select t:FD* -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test7b.v → architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset.v

 // Check that use of resets block shreg
 // neg_clk_no_enable_with_init_with_inferred_with_reset
 (* top *)
-module test7b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
+module neg_clk_no_enable_with_init_with_inferred_with_reset #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
 
@@ -24,6 +24,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test7b; select t:SRL* -assert-none";
+    wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_with_reset; select t:SRL* -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test7d.v → architecture/synth_xilinx_srl/neg_clk_no_enable_with_init_with_inferred_with_reset_var_len.v

 // Check that use of resets block shreg
 // neg_clk_no_enable_with_init_with_inferred_with_reset_var_len
 (* top *)
-module test7d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
+module neg_clk_no_enable_with_init_with_inferred_with_reset_var_len #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
 generate 
     reg [depth-1:0] int [width-1:0];
 
@@ -24,6 +24,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test7d; select t:SRL* -assert-none";
+    wire [4095:0] assert_area = "cd neg_clk_no_enable_with_init_with_inferred_with_reset_var_len; select t:SRL* -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test8.v → architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_N_width.v

 // Check multi-bit works
 // pos_clk_no_enable_no_init_not_inferred_N_width
 (* top *)
-module test8 #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
+module pos_clk_no_enable_no_init_not_inferred_N_width #(parameter width=130, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
     genvar w, d;
@@ -17,6 +17,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test8; select t:FD* -assert-none";
+    wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_N_width; select t:FD* -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test7a.v → architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset.v

 // Check that use of resets block shreg
 // pos_clk_no_enable_no_init_not_inferred_with_reset
 (* top *)
-module test7a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
+module pos_clk_no_enable_no_init_not_inferred_with_reset #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
     genvar w, d;
@@ -17,6 +17,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test7a; select t:SRL* -assert-none";
+    wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_with_reset; select t:SRL* -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test7c.v → architecture/synth_xilinx_srl/pos_clk_no_enable_no_init_not_inferred_with_reset_var_len.v

 // Check that use of resets block shreg
 // pos_clk_no_enable_no_init_not_inferred_with_reset_var_len
 (* top *)
-module test7c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
+module pos_clk_no_enable_no_init_not_inferred_with_reset_var_len #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input r, input [31:0] l, output [width-1:0] q);
 generate 
     wire [depth:0] int [width-1:0];
     genvar w, d;
@@ -19,6 +19,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test7c; select t:SRL* -assert-none";
+    wire [4095:0] assert_area = "cd pos_clk_no_enable_no_init_not_inferred_with_reset_var_len; select t:SRL* -assert-none";
 endmodule
 `endif

architecture/synth_xilinx_srl/test13a.v → architecture/synth_xilinx_srl/sr_fixed_length_other_users_port.v

@@ -2,7 +2,7 @@
 // (i.e. output port, in non flattened case)
 // sr_fixed_length_other_users_port
 (* top *)
-module test13a #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
+module sr_fixed_length_other_users_port #(parameter width=1, depth=130) (input clk, input [width-1:0] i, output [width-1:0] q, output [depth-1:0] state);
 generate 
     wire [depth:0] int [width-1:0];
     genvar w, d;
@@ -19,6 +19,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test13a; select t:SRL* -assert-count 0";
+    wire [4095:0] assert_area = "cd sr_fixed_length_other_users_port; select t:SRL* -assert-count 0";
 endmodule
 `endif

architecture/synth_xilinx_srl/test13c.v → architecture/synth_xilinx_srl/sr_fixed_length_other_users_xor.v

@@ -2,7 +2,7 @@
 // (i.e. output port, in non flattened case)
 // sr_fixed_length_other_users_xor
 (* top *)
-module test13c #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
+module sr_fixed_length_other_users_xor #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, output [width-1:0] q, output [depth-1:0] state);
 generate 
     wire [depth:0] int [width-1:0];
     genvar w, d;
@@ -19,6 +19,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test13c; select t:SRL* -assert-count 0";
+    wire [4095:0] assert_area = "cd sr_fixed_length_other_users_xor; select t:SRL* -assert-count 0";
 endmodule
 `endif

architecture/synth_xilinx_srl/test13b.v → architecture/synth_xilinx_srl/sr_var_length_other_users_port.v

@@ -2,7 +2,7 @@
 // (i.e. output port, in non flattened case)
 // sr_var_length_other_users_port
 (* top *)
-module test13b #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
+module sr_var_length_other_users_port #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
 generate 
     reg [depth-1:0] int [width-1:0];
 
@@ -26,6 +26,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test13b; select t:SRL* -assert-count 0";
+    wire [4095:0] assert_area = "cd sr_var_length_other_users_port; select t:SRL* -assert-count 0";
 endmodule
 `endif

architecture/synth_xilinx_srl/test13d.v → architecture/synth_xilinx_srl/sr_var_length_other_users_xor.v

@@ -2,7 +2,7 @@
 // (i.e. output port, in non flattened case)
 // sr_var_length_other_users_xor
 (* top *)
-module test13d #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
+module sr_var_length_other_users_xor #(parameter width=1, depth=130) (input clk, input [width-1:0] i, input e, input [31:0] l, output [width-1:0] q, output [depth-1:0] state);
 generate 
     reg [depth-1:0] int [width-1:0];
 
@@ -26,6 +26,6 @@ endmodule
 
 `ifndef _AUTOTB
 module __test ;
-    wire [4095:0] assert_area = "cd test13d; select t:SRL* -assert-count 0";
+    wire [4095:0] assert_area = "cd sr_var_length_other_users_xor; select t:SRL* -assert-count 0";
 endmodule
 `endif