Blame · misc/scripts/splice_sel_by_cell_and_sel_any_bit.ys · f1293367e38333db28a05aa9d52b22f6f297b2e2 · lvzhengyang / yosys-tests · GitLab

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splice_sel_by_cell_and_sel_any_bit.ys 84 Bytes

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Add tests for error messages in 'misc' test group.

committed 5 years ago

read_verilog ../top.v
synth
splice -sel_by_cell -sel_any_bit
tee -o result.log dump