Blame · simple/scripts/fsm.ys · e50ebb885149603dffd18289ceeb1cd7380d6075 · lvzhengyang / yosys-tests · GitLab

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First tests for pilot project

committed 6 years ago

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read_verilog ../top.v
proc
fsm_detect
fsm_extract
opt
fsm_opt
synth -top top
write_verilog synth.v