`timescale 1ns/1ps module testbench; reg clk; initial begin // $dumpfile("testbench.vcd"); // $dumpvars(0, testbench); #0 clk = 0; repeat (10000) begin #5 clk = 1; #5 clk = 0; end $display("OKAY"); end wire y; top uut(clk,1'b1,y); assert_X check_output(clk,y); endmodule