Blame · architecture/scripts/synth_xilinx_nowidelut_abc9.ys · 45c0ea8c55e0184c68b0045bd8683e25110cbee8 · lvzhengyang / yosys-tests · GitLab

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synth_xilinx_nowidelut_abc9.ys 74 Bytes

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Add new tests to 'architecture' test group

committed 5 years ago

read_verilog ../top.v
synth_xilinx -nowidelut -abc9
write_verilog synth.v