read_verilog ../top.v design -save read hierarchy -top dff proc equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46620V # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module stat select -assert-count 1 t:GP_DFF select -assert-count 2 t:GP_IBUF select -assert-count 1 t:GP_OBUF select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D design -load read hierarchy -top dffe proc equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46620V # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module stat select -assert-count 1 t:GP_3LUT select -assert-count 1 t:GP_DFF select -assert-count 3 t:GP_IBUF select -assert-count 1 t:GP_OBUF select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
