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yosys-tests
Commit abaa8979 by SergeyDegtyar
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Review and update tests for greenpak4,ice40 architectures.

parent 4b996cba
Showing with 1504 additions and 12 deletions
architecture_reviewed/Makefile
......@@ -39,6 +39,12 @@ $(eval $(call template,synth_ecp5,synth_ecp5 synth_ecp5_top synth_ecp5_blif synt
$(eval $(call template,synth_efinix, synth_efinix synth_efinix_edif synth_efinix_json synth_efinix_noflatten synth_efinix_retime synth_efinix_run synth_efinix_top synth_efinix_fulladder))
#gowin
$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe ))
$(eval $(call template,synth_gowin,synth_gowin synth_gowin_top synth_gowin_vout synth_gowin_run synth_gowin_retime synth_gowin_nobram synth_gowin_noflatten synth_gowin_nodram synth_gowin_nodffe))
#greenpak4
$(eval $(call template,synth_greenpak4,synth_greenpak4 synth_greenpak4_top synth_greenpak4_json synth_greenpak4_run synth_greenpak4_noflatten synth_greenpak4_retime synth_greenpak4_part621 synth_greenpak4_part620 synth_greenpak4_part140 synth_greenpak4_fully_selected_fail synth_greenpak4_invalid_part_fail synth_greenpak4_adffs synth_greenpak4_adffsr synth_greenpak4_gp_dffs synth_greenpak4_inv_inputs))
#ice40
$(eval $(call template,synth_ice40,synth_ice40 synth_ice40_top synth_ice40_blif synth_ice40_edif synth_ice40_json synth_ice40_run synth_ice40_noflatten synth_ice40_flatten synth_ice40_retime synth_ice40_nocarry synth_ice40_nodffe synth_ice40_nobram synth_ice40_abc2 synth_ice40_vpr synth_ice40_relut synth_ice40_dsp synth_ice40_min_ce synth_ice40_noabc synth_ice40_device_u synth_ice40_device_lp synth_ice40_device_hx synth_ice40_opt synth_ice40_fully_selected_fail synth_ice40_device_unknown_fail synth_ice40_abc9 synth_ice40_abc9_retime_fail synth_ice40_mem_init synth_ice40_wide_ffs))
.PHONY: all clean
architecture_reviewed/run.sh
......@@ -11,6 +11,16 @@ cd $1/work_$2
touch .start
#
if [ -f ../run-test.sh ]; then
../run-test.sh
if [ $? != 0 ] ; then
echo FAIL > ${1}_${2}.status
else
echo PASS > ${1}_${2}.status
fi
touch .stamp
exit
fi
if [[ $2 =~ "_fail" ]]; then
#4 - An error expected
if yosys -ql yosys.log ../$2.ys; then
......
architecture_reviewed/synth_ecp5/synth_ecp5_nodsp.ys
read_verilog ../top.v
read_verilog ../top_dsp.v
design -save read
hierarchy -top dff
hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -nodsp # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
select -assert-count 1 t:MULT18X18D
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:MULT18X18D t:TRELLIS_FF %% t:* %D
design -load read
hierarchy -top dffe
hierarchy -top top
proc
equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 -nodsp # equivalency check
equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 -nodsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:TRELLIS_FF
select -assert-none t:TRELLIS_FF %% t:* %D
select -assert-count 4 t:LUT4
select -assert-count 8 t:TRELLIS_FF
select -assert-none t:LUT4 t:TRELLIS_FF %% t:* %D
architecture_reviewed/synth_ecp5/top_dsp.v 0 → 100644
(* top *)
module top #(parameter AW=2, BW=2, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, (* keep *) output reg [AW+BW-1:0] P);
(* keep *) reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
architecture_reviewed/synth_greenpak4/synth_greenpak4.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_adffs.ys 0 → 100644
read_verilog ../top_adffs.v
design -save read
hierarchy -top dffr
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSR
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSR t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffs
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffs # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSR
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSR t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_adffsr.ys 0 → 100644
read_verilog ../top_dffsr.v
design -save read
hierarchy -top dffsr
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffsr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:$_DFFSR_PPP_
select -assert-count 1 t:GP_2LUT
select -assert-count 4 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:$_DFFSR_PPP_ t:GP_2LUT t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top ndffnsnr
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd ndffnsnr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:$_DFFSR_NPP_
select -assert-count 1 t:GP_2LUT
select -assert-count 4 t:GP_IBUF
select -assert-count 1 t:GP_INV
select -assert-count 1 t:GP_OBUF
select -assert-none t:$_DFFSR_NPP_ t:GP_2LUT t:GP_IBUF t:GP_INV t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture_reviewed/synth_greenpak4/synth_greenpak4_gp_dffs.ys 0 → 100644
read_verilog ../top_gp_dffs.v
design -save read
hierarchy -top gp_dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFI
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFI t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top gp_dffr
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_dffr # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSRI
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSRI t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top gp_dffs
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_dffs # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSRI
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSRI t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top gp_dffsi
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_dffsi # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFFSR
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFFSR t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top gp_latchs
proc
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd gp_latchs # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DLATCHSRI
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DLATCHSRI t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_inv_inputs.ys 0 → 100644
read_verilog ../top_inv_inputs.v
hierarchy -top top
proc
flatten
equiv_opt -map +/greenpak4/cells_sim.v synth_greenpak4 -top top # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:GP_DFFSRI
select -assert-count 7 t:GP_IBUF
select -assert-count 1 t:GP_INV
select -assert-count 4 t:GP_OBUF
select -assert-none t:GP_DFFSRI t:GP_IBUF t:GP_INV t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_json.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_part140.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46140V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46140V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_part620.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46620V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46620V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_part621.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46621V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -part SLG46621V # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/synth_greenpak4_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_DFF
select -assert-count 2 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/greenpak4/cells_sim.v synth_greenpak4 -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:GP_3LUT
select -assert-count 1 t:GP_DFF
select -assert-count 3 t:GP_IBUF
select -assert-count 1 t:GP_OBUF
select -assert-none t:GP_3LUT t:GP_DFF t:GP_IBUF t:GP_OBUF %% t:* %D
architecture_reviewed/synth_greenpak4/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
architecture_reviewed/synth_greenpak4/top_adffs.v 0 → 100644
module dffs
( input d, clk, pre, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge pre )
if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
module dffr
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, negedge clr )
if ( !clr )
q <= 1'b0;
else
q <= d;
endmodule
architecture_reviewed/synth_greenpak4/top_dffsr.v 0 → 100644
module dffsr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge pre, posedge clr )
if ( clr )
q <= 1'b0;
else if ( pre )
q <= 1'b1;
else
q <= d;
endmodule
module ndffnsnr
( input d, clk, pre, clr, output reg q );
initial begin
q = 0;
end
always @( negedge clk, negedge pre, negedge clr )
if ( !clr )
q <= 1'b0;
else if ( !pre )
q <= 1'b1;
else
q <= d;
endmodule
architecture_reviewed/synth_greenpak4/top_gp_dffs.v 0 → 100644
module gp_dff
( input d, input clk, clr, output reg q );
wire nq;
GP_DFF u_gp_dffr (d,clk,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffr
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFR u_gp_dffr (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffs
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFS u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_dffsi
( input d, input clk, clr, output reg q );
wire nq;
GP_DFFSI u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
module gp_latchs
( input d, input clk, clr, output reg q );
wire nq;
GP_DLATCHS u_gp_dffs (d,clk,clr,nq);
GP_INV u_gp_inv (nq,q);
endmodule
architecture_reviewed/synth_greenpak4/top_inv_inputs.v 0 → 100644
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module top (
input clk,
input clr,
input pre,
input [3:0] a,
output [3:0] b
);
adff u_adff (
.clk (~clk ),
.clr (~clr),
.d (~a ),
.q (b )
);
endmodule
architecture_reviewed/synth_ice40/synth_ice40.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_abc2.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_abc9.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_abc9_retime_fail.pat 0 → 100644
ERROR: -retime option not currently compatible with -abc9!
architecture_reviewed/synth_ice40/synth_ice40_abc9_retime_fail.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -abc9 -retime
architecture_reviewed/synth_ice40/synth_ice40_blif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -blif blif.blif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_device_hx.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device hx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device hx # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_device_lp.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device lp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device lp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_device_u.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device u # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -device u # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_device_unknown_fail.pat 0 → 100644
ERROR: Invalid or no device specified: 'unknown'
architecture_reviewed/synth_ice40/synth_ice40_device_unknown_fail.ys 0 → 100644
read_verilog ../top.v
synth_ice40 -device unknown
write_verilog synth.v
architecture_reviewed/synth_ice40/synth_ice40_dsp.ys 0 → 100644
read_verilog ../top_dsp.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 10 t:SB_CARRY
select -assert-count 32 t:SB_DFF
select -assert-count 159 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 16 t:SB_DFF
select -assert-count 1 t:SB_MAC16
select -assert-none t:SB_DFF t:SB_MAC16 %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_edif.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -edif edif.edif # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_flatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -flatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_fully_selected_fail.pat 0 → 100644
ERROR: This command only operates on fully selected designs!
architecture_reviewed/synth_ice40/synth_ice40_fully_selected_fail.ys 0 → 100644
read_verilog ../top.v
select dffe
synth_ice40
write_verilog synth.v
architecture_reviewed/synth_ice40/synth_ice40_json.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -json json.json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_mem_init.ys 0 → 100644
read_verilog ../top_mem.v
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
stat
select -assert-count 2 t:SB_RAM40_4K
select -assert-none t:SB_RAM40_4K %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_min_ce.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dffe_min_ce_use 2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dffe_min_ce_use 2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_LUT4 %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_noabc.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -noabc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -noabc # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_nobram.ys 0 → 100644
read_verilog ../top_dpram.v
design -save read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 1 t:SB_RAM40_4K
select -assert-none t:SB_RAM40_4K %% t:* %D
design -load read
hierarchy -top top
proc
memory -nomap
equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 -nobram
memory
opt -full
miter -equiv -flatten -make_assert -make_outputs gold gate miter
#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
design -load postopt
cd top
select -assert-count 6 t:SB_DFF
select -assert-count 384 t:SB_DFFE
select -assert-count 368 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_DFFE t:SB_LUT4 %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_nocarry.ys 0 → 100644
read_verilog ../top_dsp_nocarry.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_CARRY
select -assert-count 8 t:SB_DFF
select -assert-count 6 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top top
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -nocarry # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 8 t:SB_DFF
select -assert-count 4 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_LUT4 %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_nodffe.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -nodffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -nodffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-count 1 t:SB_LUT4
select -assert-none t:SB_DFF t:SB_LUT4 %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_noflatten.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -noflatten # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_opt.ys 0 → 100644
read_verilog ../top_dsp_nocarry.v
design -save read
hierarchy -top top
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_CARRY
select -assert-count 8 t:SB_DFF
select -assert-count 6 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top top
proc
synth_ice40
equiv_opt -assert -map +/ice40/cells_sim.v ice40_opt # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_CARRY
select -assert-count 8 t:SB_DFF
select -assert-count 6 t:SB_LUT4
select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_relut.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -relut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -relut # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_retime.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -retime # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_run.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -run begin:json # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_top.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -top dff # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -top dffe # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_vpr.ys 0 → 100644
read_verilog ../top.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFF
select -assert-none t:SB_DFF %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -vpr # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-none t:SB_DFFE %% t:* %D
architecture_reviewed/synth_ice40/synth_ice40_wide_ffs.ys 0 → 100644
read_verilog ../top_wide_ffs.v
design -save read
hierarchy -top dff
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_DFFSR
select -assert-count 2 t:SB_DFFSS
select -assert-none t:SB_DFFSR t:SB_DFFSS %% t:* %D
design -load read
hierarchy -top adff
proc
#equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd adff # Constrain all select calls below inside the top module
stat
select -assert-count 2 t:SB_DFFR
select -assert-count 2 t:SB_DFFS
select -assert-none t:SB_DFFR t:SB_DFFS %% t:* %D
design -load read
hierarchy -top dffe
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
stat
select -assert-count 4 t:SB_DFFE
select -assert-count 2 t:SB_LUT4
select -assert-none t:SB_DFFE t:SB_LUT4 %% t:* %D
design -load read
hierarchy -top dffse
proc
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffse # Constrain all select calls below inside the top module
stat
select -assert-count 1 t:SB_DFFE
select -assert-count 2 t:SB_DFFESR
select -assert-count 1 t:SB_DFFESS
select -assert-count 4 t:SB_LUT4
select -assert-none t:SB_DFFE t:SB_DFFESR t:SB_DFFESS t:SB_LUT4 %% t:* %D
architecture_reviewed/synth_ice40/top.v 0 → 100644
module dff
( input d, clk, output reg q );
initial begin
q = 0;
end
always @( posedge clk )
q <= d;
endmodule
module dffe
( input d, clk, en, output reg q );
initial begin
q = 0;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module adff
( input d, clk, clr, output reg q );
initial begin
q = 0;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 1'b0;
else
q <= d;
endmodule
architecture_reviewed/synth_ice40/top_dpram.v 0 → 100644
/*
Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72].
*/
module top (din, write_en, waddr, wclk, raddr, rclk, dout);
parameter addr_width = 6;
parameter data_width = 6;
input [addr_width-1:0] waddr, raddr;
input [data_width-1:0] din;
input write_en, wclk, rclk;
output [data_width-1:0] dout;
reg [data_width-1:0] dout;
reg [data_width-1:0] mem [(1<<addr_width)-1:0]
/* synthesis syn_ramstyle = "no_rw_check" */ ;
always @(posedge wclk) // Write memory.
begin
if (write_en)
mem[waddr] <= din; // Using write address bus.
end
always @(posedge rclk) // Read memory.
begin
dout <= mem[raddr]; // Using read address bus.
end
endmodule
architecture_reviewed/synth_ice40/top_dsp.v 0 → 100644
(* top *)
module top #(parameter AW=8, BW=8, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, (* keep *) output reg [AW+BW-1:0] P);
(* keep *) reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
architecture_reviewed/synth_ice40/top_dsp_nocarry.v 0 → 100644
(* top *)
module top #(parameter AW=2, BW=2, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, (* keep *) output reg [AW+BW-1:0] P);
(* keep *) reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
architecture_reviewed/synth_ice40/top_mem.v 0 → 100644
module top
(
input [7:0] data_a,
input [6:1] addr_a,
input we_a, clk,
output reg [7:0] q_a,
output reg [15:0] q_b,
output reg [15:0] q_c
);
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("../init.txt")
) \ram.0.0.0 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
.RCLK(clk),
.RCLKE(1'h1),
.RDATA(q_b),
.RE(1'h1),
.WADDR({ 5'h00, addr_a }),
.WCLK(clk),
.WCLKE(we_a),
.WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
.WE(1'h1)
);
SB_RAM40_4K #(
.READ_MODE(2'h1),
.WRITE_MODE(2'h1),
.INIT_FILE("../init1.txt")
) \ram.0.0.1 (
.MASK(16'hxxxx),
.RADDR({ 5'h00, addr_a }),
.RCLK(clk),
.RCLKE(1'h1),
.RDATA(q_c),
.RE(1'h1),
.WADDR({ 5'h00, addr_a }),
.WCLK(clk),
.WCLKE(we_a),
.WDATA({ 1'hx, data_a[7], 1'hx, data_a[6], 1'hx, data_a[5], 1'hx, data_a[4], 1'hx, data_a[3], 1'hx, data_a[2], 1'hx, data_a[1], 1'hx, data_a[0] }),
.WE(1'h1)
);
endmodule
architecture_reviewed/synth_ice40/top_wide_ffs.v 0 → 100644
module dff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module adff
( input [3:0] d, input clk, clr, output reg [3:0] q );
initial begin
q = 4'b0000;
end
always @( posedge clk, posedge clr )
if ( clr )
q <= 4'b0110;
else
q <= d;
endmodule
module dffe
( input [3:0] d, input clk, en, output reg [3:0] q );
initial begin
q = 4'b0010;
end
always @( posedge clk)
if ( en )
q <= d;
endmodule
module dffse
( input [3:0] d, input clk, en, pre, output reg [3:0] q );
initial begin
q = 1;
end
always @( posedge clk )
if ( !pre )
q <= 4'b0101;
else
if ( en )
q <= d;
endmodule
architecture_reviewed/synth_ice40_dsp/assert_area.py 0 → 100755
#!/usr/bin/python3
import glob
import re
import os
re_mux = re.compile(r'mul_(\d+)(s?)_(\d+)(s?)_(A?B?P?)_A?B?P?\.v')
for fn in glob.glob('*.v'):
m = re_mux.match(fn)
if not m: continue
macc = False
A,B = map(int, m.group(1,3))
Asigned, Bsigned = m.group(2,4)
Areg = 'A' in m.group(5)
Breg = 'B' in m.group(5)
Preg = 'P' in m.group(5)
X = (A+14) // 16
Y = (B+14) // 16
count_MAC = X * Y
count_DFF = 0
if A % 16 > 1 and B % 16 > 1 and (A % 16 + B % 16) < 11:
count_MAC -= 1
if Areg or Breg:
count_DFF += A%16 + B%16
else:
# TODO: Tighter bounds on count_DFF
if (Areg or Breg) and (A % 16 == 1 or B % 16 == 1):
count_DFF += A + B
if Preg and (A > 16 or B > 16):
count_DFF += A + B
if macc:
count_DFF += 5 # In my testcases, accumulator is always
# 5bits bigger than multiplier result
elif (A > 16) ^ (B > 16):
count_DFF -= 1 # For pure multipliers with just one big dimension,
# expect last slice to absorb at least one register
# TODO: More assert on number of CARRY and LUTs
count_CARRY = ''
if (A <= 16 or B <= 16) and A % 16 != 1 and B % 16 != 1:
count_CARRY = '; select t:SB_CARRY -assert-none; select t:SB_LUT -assert-none';
count_DFF = 0
bn,_ = os.path.splitext(fn)
with open(fn, 'a') as f:
print('''
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd {0}; select t:SB_MAC16 -assert-count {1}; select t:SB_DFF* -assert-max {2}{3}";
endmodule
`endif
'''.format(os.path.splitext(fn)[0], count_MAC, count_DFF, count_CARRY), file=f)
architecture_reviewed/synth_ice40_dsp/generate_mul.py 0 → 100644
#!/usr/bin/env python3
from common_mul import gen_mul
ARange = ['16','16s','17','17s','24','24s','31','31s','32','32s','33','33s','47','47s','48','48s','49','49s']
BRange = ['15','15s','16','16s','17','17s','24','24s','31','31s','32','32s']
if __name__ == "__main__":
gen_mul(ARange, BRange, "ABP")
architecture_reviewed/synth_ice40_dsp/mul_16_16_keepABP_.v 0 → 100644
(* top *)
module mul_16_16_keepABP_ #(parameter AW=16, BW=16, AREG=1, BREG=1, PREG=1) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, (* keep *) output reg [AW+BW-1:0] P);
(* keep *) reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd mul_16_16_keepABP_; select t:SB_MAC16 -assert-count 1; select t:SB_DFF* -assert-count 32";
endmodule
`endif
architecture_reviewed/synth_ice40_dsp/mul_32_32_keepB_.v 0 → 100644
(* top *)
module mul_32_32_keepB_ #(parameter AW=32, BW=32, AREG=1, BREG=1, PREG=0) (input clk, CEA, CEB, CEP, input [AW-1:0] A, input [BW-1:0] B, output reg [AW+BW-1:0] P);
reg [AW-1:0] Ar;
(* keep *) reg [BW-1:0] Br;
generate
if (AREG) begin
always @(posedge clk) if (1) Ar <= A;
end
else
always @* Ar <= A;
if (BREG) begin
always @(posedge clk) if (1) Br <= B;
end
else
always @* Br <= B;
if (PREG) begin
always @(posedge clk) if (1) P <= Ar * Br;
end
else
always @* P <= Ar * Br;
endgenerate
endmodule
`ifndef _AUTOTB
module __test ;
wire [4095:0] assert_area = "cd mul_32_32_keepB_; select t:SB_MAC16 -assert-count 4; select t:SB_DFF* -assert-count 32";
endmodule
`endif
architecture_reviewed/synth_ice40_dsp/run-test.sh 0 → 100755
#!/bin/bash
set -e
OPTIND=1
seed="" # default to no seed specified
while getopts "S:" opt
do
case "$opt" in
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
seed="SEED=$arg" ;;
esac
done
shift "$((OPTIND-1))"
# check for Icarus Verilog
if ! which iverilog > /dev/null ; then
echo "$0: Error: Icarus Verilog 'iverilog' not found."
exit 1
fi
wget https://raw.githubusercontent.com/YosysHQ/yosys-bench/master/verilog/benchmarks_small/mul/common.py -O common_mul.py -o /dev/null
#cp ~/yosys/yosys-bench/verilog/benchmarks_small/mul/common.py common_mul.py
PYTHONPATH=".:$PYTHONPATH" python3 ../generate_mul.py
python3 ../assert_area.py
cp ../*.v .
${MAKE:-make} -f ../../../../tools/autotest.mk $seed *.v EXTRA_FLAGS="\
-p 'design -copy-to __test __test; \
synth_ice40 -dsp; \
design -copy-from __test *; \
select -assert-any __test; \
script -scriptwire __test/w:assert_area'\
-l ../../../../../techlibs/ice40/cells_sim.v"
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