Commits · cb42f37bb21e5b5fa094bac3096b20f42a275fc8 · lvzhengyang / sv2v · GitLab

10 Feb, 2019 3 commits
- removed support for inital and delays · cb42f37b
  Zachary Snow committed Feb 10, 2019
  
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- arguably cleaner Show output for AST modules · 767b05cd
  Zachary Snow committed Feb 10, 2019
  
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- support for reduction ops, non-named/non-identifier module instantiation arguments, always @* · 14ba5dae
  Zachary Snow committed Feb 10, 2019
  
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09 Feb, 2019 2 commits
- cleanup of port decl parsing · 5b336439
  Zachary Snow committed Feb 09, 2019
  
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- hacky, preliminary support for port declarations in module header · ebd7ae67
  Zachary Snow committed Feb 09, 2019
  
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08 Feb, 2019 6 commits
- updated build procedure · 0f263807
  Zachary Snow committed Feb 08, 2019
  
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- updated LICENSE to reflect fork · fb8f088b
  Zachary Snow committed Feb 08, 2019
  
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- Basic build setup! · 8bd58e96
  Zachary Snow committed Feb 08, 2019
  
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- Refactor project setup for our purposes · b46009af
  Zachary Snow committed Feb 08, 2019
  
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- Fix compiliation; trailing whitespace; added .gitignore · bfafea5d
  Zachary Snow committed Feb 07, 2019
  
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- Initial commit: fork of https://github.com/tomahawkins/verilog · 363ca80a
  Zachary Snow committed Feb 07, 2019
  
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