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lvzhengyang
sv2v
Commits
c840bcd6
Commit
c840bcd6
authored
Dec 24, 2022
by
Zachary Snow
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prefer larger base when concatenating numbers
parent
96a108de
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src/Language/SystemVerilog/AST/Number.hs
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src/Language/SystemVerilog/AST/Number.hs
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c840bcd6
...
@@ -454,7 +454,7 @@ instance Semigroup Number where
...
@@ -454,7 +454,7 @@ instance Semigroup Number where
where
where
size
=
size1
+
size2
size
=
size1
+
size2
signed
=
False
signed
=
False
base
=
selectBase
(
m
in
base1
base2
)
values
kinds
base
=
selectBase
(
m
ax
base1
base2
)
values
kinds
trim
=
flip
mod
.
(
2
^
)
trim
=
flip
mod
.
(
2
^
)
values
=
trim
size2
values2
+
shiftL
(
trim
size1
values1
)
size2
values
=
trim
size2
values2
+
shiftL
(
trim
size1
values1
)
size2
kinds
=
trim
size2
kinds2
+
shiftL
(
trim
size1
kinds1
)
size2
kinds
=
trim
size2
kinds2
+
shiftL
(
trim
size1
kinds1
)
size2
...
...
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