Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
69bc64ed
Commit
69bc64ed
authored
May 31, 2021
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
remove legacy ordered binding handling in logic conversion
parent
13c84e4c
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
5 additions
and
16 deletions
+5
-16
src/Convert/Logic.hs
+5
-16
No files found.
src/Convert/Logic.hs
View file @
69bc64ed
...
@@ -130,18 +130,17 @@ traverseModuleItem ports scopes =
...
@@ -130,18 +130,17 @@ traverseModuleItem ports scopes =
where
where
comment
=
MIPackageItem
$
Decl
$
CommentDecl
comment
=
MIPackageItem
$
Decl
$
CommentDecl
"rewrote reg-to-output bindings"
"rewrote reg-to-output bindings"
(
bindings'
,
newItemsList
)
=
(
bindings'
,
newItemsList
)
=
unzip
$
map
fixBinding
bindings
unzip
$
map
(
uncurry
fixBinding
)
$
zip
bindings
[
0
..
]
newItems
=
concat
newItemsList
newItems
=
concat
newItemsList
fixBinding
::
PortBinding
->
Int
->
(
PortBinding
,
[
ModuleItem
])
fixBinding
::
PortBinding
->
(
PortBinding
,
[
ModuleItem
])
fixBinding
(
portName
,
expr
)
portIdx
=
fixBinding
(
portName
,
expr
)
=
if
not
outputBound
||
not
usesReg
if
not
outputBound
||
not
usesReg
then
((
portName
,
expr
),
[]
)
then
((
portName
,
expr
),
[]
)
else
((
portName
,
tmpExpr
),
items
)
else
((
portName
,
tmpExpr
),
items
)
where
where
outputBound
=
portDir
==
Just
Output
outputBound
=
portDir
==
Just
Output
usesReg
=
Just
True
==
fmap
isReg
(
exprToLHS
expr
)
usesReg
=
Just
True
==
fmap
isReg
(
exprToLHS
expr
)
portDir
=
lookupPortDir
portName
portIdx
portDir
=
maybeModulePorts
>>=
lookup
portName
tmp
=
"sv2v_tmp_"
++
instanceName
++
"_"
++
portName
tmp
=
"sv2v_tmp_"
++
instanceName
++
"_"
++
portName
tmpExpr
=
Ident
tmp
tmpExpr
=
Ident
tmp
t
=
Net
(
NetType
TWire
)
Unspecified
t
=
Net
(
NetType
TWire
)
Unspecified
...
@@ -155,17 +154,7 @@ traverseModuleItem ports scopes =
...
@@ -155,17 +154,7 @@ traverseModuleItem ports scopes =
error
$
"bad non-lhs, non-net expr "
error
$
"bad non-lhs, non-net expr "
++
show
expr
++
" connected to output port "
++
show
expr
++
" connected to output port "
++
portName
++
" of "
++
instanceName
++
portName
++
" of "
++
instanceName
lookupPortDir
::
Identifier
->
Int
->
Maybe
Direction
maybeModulePorts
=
Map
.
lookup
moduleName
ports
lookupPortDir
""
portIdx
=
case
Map
.
lookup
moduleName
ports
of
Nothing
->
Nothing
Just
l
->
if
portIdx
>=
length
l
then
Nothing
else
Just
$
snd
$
l
!!
portIdx
lookupPortDir
portName
_
=
case
Map
.
lookup
moduleName
ports
of
Nothing
->
Nothing
Just
l
->
lookup
portName
l
fixModuleItem
other
=
other
fixModuleItem
other
=
other
traverseDeclM
::
Decl
->
ST
Decl
traverseDeclM
::
Decl
->
ST
Decl
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment