Commit 3807ab67 by Zachary Snow

handle adding packed dimensions to byte, shortint, and longint

parent ceb384f6
...@@ -17,20 +17,6 @@ convert = ...@@ -17,20 +17,6 @@ convert =
traverseTypes convertType traverseTypes convertType
convertType :: Type -> Type convertType :: Type -> Type
convertType (IntegerAtom TInt sg) = baseType sg Signed 32 convertType (IntegerAtom kw sg) = elaborateIntegerAtom $ IntegerAtom kw sg
convertType (IntegerAtom TShortint sg) = baseType sg Signed 16
convertType (IntegerAtom TLongint sg) = baseType sg Signed 64
convertType (IntegerAtom TByte sg) = baseType sg Unspecified 8
convertType (IntegerVector TBit sg rs) = IntegerVector TLogic sg rs convertType (IntegerVector TBit sg rs) = IntegerVector TLogic sg rs
convertType other = other convertType other = other
-- makes a integer "compatible" type with the given signing, base signing and
-- size; if not unspecified, the first signing overrides the second
baseType :: Signing -> Signing -> Int -> Type
baseType sgOverride sgBase size =
IntegerVector TReg sg [(Number hi, Number "0")]
where
hi = show (size - 1)
sg = if sgOverride /= Unspecified
then sgOverride
else sgBase
...@@ -18,6 +18,7 @@ module Language.SystemVerilog.AST.Type ...@@ -18,6 +18,7 @@ module Language.SystemVerilog.AST.Type
, NonIntegerType (..) , NonIntegerType (..)
, typeRanges , typeRanges
, nullRange , nullRange
, elaborateIntegerAtom
) where ) where
import Text.Printf (printf) import Text.Printf (printf)
...@@ -98,12 +99,32 @@ nullRange t [(Number "0", Number "0")] = t ...@@ -98,12 +99,32 @@ nullRange t [(Number "0", Number "0")] = t
nullRange (IntegerAtom TInteger sg) rs = nullRange (IntegerAtom TInteger sg) rs =
-- integer arrays are allowed in SystemVerilog but not in Verilog -- integer arrays are allowed in SystemVerilog but not in Verilog
IntegerVector TBit sg (rs ++ [(Number "31", Number "0")]) IntegerVector TBit sg (rs ++ [(Number "31", Number "0")])
nullRange (IntegerAtom TInt sg) rs = nullRange t rs1 =
-- int arrays are allowed in SystemVerilog but not in Verilog if t == t'
IntegerVector TBit sg (rs ++ [(Number "31", Number "0")]) then error $ "non-vector type " ++ show t ++
nullRange t rs = " cannot have packed dimesions:" ++ show rs1
error $ "non-vector type " ++ show t ++ else tf $ rs1 ++ rs2
" cannot have a packed dimesions:" ++ show rs where
t' = elaborateIntegerAtom t
(tf, rs2) = typeRanges t'
elaborateIntegerAtom :: Type -> Type
elaborateIntegerAtom (IntegerAtom TInt sg) = baseIntType sg Signed 32
elaborateIntegerAtom (IntegerAtom TShortint sg) = baseIntType sg Signed 16
elaborateIntegerAtom (IntegerAtom TLongint sg) = baseIntType sg Signed 64
elaborateIntegerAtom (IntegerAtom TByte sg) = baseIntType sg Unspecified 8
elaborateIntegerAtom other = other
-- makes a integer "compatible" type with the given signing, base signing and
-- size; if not unspecified, the first signing overrides the second
baseIntType :: Signing -> Signing -> Int -> Type
baseIntType sgOverride sgBase size =
IntegerVector TReg sg [(Number hi, Number "0")]
where
hi = show (size - 1)
sg = if sgOverride /= Unspecified
then sgOverride
else sgBase
data Signing data Signing
= Unspecified = Unspecified
......
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