Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
S
sv2v
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
lvzhengyang
sv2v
Commits
3807ab67
Commit
3807ab67
authored
Sep 30, 2019
by
Zachary Snow
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
handle adding packed dimensions to byte, shortint, and longint
parent
ceb384f6
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
28 additions
and
21 deletions
+28
-21
src/Convert/IntTypes.hs
+1
-15
src/Language/SystemVerilog/AST/Type.hs
+27
-6
No files found.
src/Convert/IntTypes.hs
View file @
3807ab67
...
...
@@ -17,20 +17,6 @@ convert =
traverseTypes
convertType
convertType
::
Type
->
Type
convertType
(
IntegerAtom
TInt
sg
)
=
baseType
sg
Signed
32
convertType
(
IntegerAtom
TShortint
sg
)
=
baseType
sg
Signed
16
convertType
(
IntegerAtom
TLongint
sg
)
=
baseType
sg
Signed
64
convertType
(
IntegerAtom
TByte
sg
)
=
baseType
sg
Unspecified
8
convertType
(
IntegerAtom
kw
sg
)
=
elaborateIntegerAtom
$
IntegerAtom
kw
sg
convertType
(
IntegerVector
TBit
sg
rs
)
=
IntegerVector
TLogic
sg
rs
convertType
other
=
other
-- makes a integer "compatible" type with the given signing, base signing and
-- size; if not unspecified, the first signing overrides the second
baseType
::
Signing
->
Signing
->
Int
->
Type
baseType
sgOverride
sgBase
size
=
IntegerVector
TReg
sg
[(
Number
hi
,
Number
"0"
)]
where
hi
=
show
(
size
-
1
)
sg
=
if
sgOverride
/=
Unspecified
then
sgOverride
else
sgBase
src/Language/SystemVerilog/AST/Type.hs
View file @
3807ab67
...
...
@@ -18,6 +18,7 @@ module Language.SystemVerilog.AST.Type
,
NonIntegerType
(
..
)
,
typeRanges
,
nullRange
,
elaborateIntegerAtom
)
where
import
Text.Printf
(
printf
)
...
...
@@ -98,12 +99,32 @@ nullRange t [(Number "0", Number "0")] = t
nullRange
(
IntegerAtom
TInteger
sg
)
rs
=
-- integer arrays are allowed in SystemVerilog but not in Verilog
IntegerVector
TBit
sg
(
rs
++
[(
Number
"31"
,
Number
"0"
)])
nullRange
(
IntegerAtom
TInt
sg
)
rs
=
-- int arrays are allowed in SystemVerilog but not in Verilog
IntegerVector
TBit
sg
(
rs
++
[(
Number
"31"
,
Number
"0"
)])
nullRange
t
rs
=
error
$
"non-vector type "
++
show
t
++
" cannot have a packed dimesions:"
++
show
rs
nullRange
t
rs1
=
if
t
==
t'
then
error
$
"non-vector type "
++
show
t
++
" cannot have packed dimesions:"
++
show
rs1
else
tf
$
rs1
++
rs2
where
t'
=
elaborateIntegerAtom
t
(
tf
,
rs2
)
=
typeRanges
t'
elaborateIntegerAtom
::
Type
->
Type
elaborateIntegerAtom
(
IntegerAtom
TInt
sg
)
=
baseIntType
sg
Signed
32
elaborateIntegerAtom
(
IntegerAtom
TShortint
sg
)
=
baseIntType
sg
Signed
16
elaborateIntegerAtom
(
IntegerAtom
TLongint
sg
)
=
baseIntType
sg
Signed
64
elaborateIntegerAtom
(
IntegerAtom
TByte
sg
)
=
baseIntType
sg
Unspecified
8
elaborateIntegerAtom
other
=
other
-- makes a integer "compatible" type with the given signing, base signing and
-- size; if not unspecified, the first signing overrides the second
baseIntType
::
Signing
->
Signing
->
Int
->
Type
baseIntType
sgOverride
sgBase
size
=
IntegerVector
TReg
sg
[(
Number
hi
,
Number
"0"
)]
where
hi
=
show
(
size
-
1
)
sg
=
if
sgOverride
/=
Unspecified
then
sgOverride
else
sgBase
data
Signing
=
Unspecified
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment