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lvzhengyang
sv2v
Commits
190c2488
Commit
190c2488
authored
Jul 07, 2021
by
Zachary Snow
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Plain Diff
remove unused typeclass derivations
parent
2f860ff2
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4 changed files
with
8 additions
and
10 deletions
+8
-10
src/Job.hs
+3
-3
src/Language/SystemVerilog/AST/Op.hs
+1
-1
src/Language/SystemVerilog/AST/Type.hs
+4
-4
src/Language/SystemVerilog/Parser/Tokens.hs
+0
-2
No files found.
src/Job.hs
View file @
190c2488
...
@@ -24,13 +24,13 @@ data Exclude
...
@@ -24,13 +24,13 @@ data Exclude
|
Interface
|
Interface
|
Logic
|
Logic
|
Succinct
|
Succinct
deriving
(
Show
,
Typeable
,
Data
,
Eq
)
deriving
(
Typeable
,
Data
,
Eq
)
data
Write
data
Write
=
Stdout
=
Stdout
|
Adjacent
|
Adjacent
|
File
FilePath
|
File
FilePath
deriving
(
Show
,
Typeable
,
Data
,
Eq
)
deriving
(
Typeable
,
Data
)
data
Job
=
Job
data
Job
=
Job
{
files
::
[
FilePath
]
{
files
::
[
FilePath
]
...
@@ -43,7 +43,7 @@ data Job = Job
...
@@ -43,7 +43,7 @@ data Job = Job
,
verbose
::
Bool
,
verbose
::
Bool
,
write
::
Write
,
write
::
Write
,
writeRaw
::
String
,
writeRaw
::
String
}
deriving
(
Show
,
Typeable
,
Data
)
}
deriving
(
Typeable
,
Data
)
version
::
String
version
::
String
version
=
version
=
...
...
src/Language/SystemVerilog/AST/Op.hs
View file @
190c2488
...
@@ -102,7 +102,7 @@ data AsgnOp
...
@@ -102,7 +102,7 @@ data AsgnOp
=
AsgnOpEq
=
AsgnOpEq
|
AsgnOpNonBlocking
|
AsgnOpNonBlocking
|
AsgnOp
BinOp
|
AsgnOp
BinOp
deriving
(
Eq
,
Ord
)
deriving
Eq
instance
Show
AsgnOp
where
instance
Show
AsgnOp
where
show
AsgnOpEq
=
"="
show
AsgnOpEq
=
"="
...
...
src/Language/SystemVerilog/AST/Type.hs
View file @
190c2488
...
@@ -226,7 +226,7 @@ data Strength
...
@@ -226,7 +226,7 @@ data Strength
=
DefaultStrength
=
DefaultStrength
|
DriveStrength
Strength0
Strength1
|
DriveStrength
Strength0
Strength1
|
ChargeStrength
ChargeStrength
|
ChargeStrength
ChargeStrength
deriving
(
Eq
,
Ord
)
deriving
Eq
instance
Show
Strength
where
instance
Show
Strength
where
show
DefaultStrength
=
""
show
DefaultStrength
=
""
...
@@ -239,7 +239,7 @@ data Strength0
...
@@ -239,7 +239,7 @@ data Strength0
|
Pull0
|
Pull0
|
Weak0
|
Weak0
|
Highz0
|
Highz0
deriving
(
Eq
,
Ord
)
deriving
Eq
instance
Show
Strength0
where
instance
Show
Strength0
where
show
Supply0
=
"supply0"
show
Supply0
=
"supply0"
...
@@ -254,7 +254,7 @@ data Strength1
...
@@ -254,7 +254,7 @@ data Strength1
|
Pull1
|
Pull1
|
Weak1
|
Weak1
|
Highz1
|
Highz1
deriving
(
Eq
,
Ord
)
deriving
Eq
instance
Show
Strength1
where
instance
Show
Strength1
where
show
Supply1
=
"supply1"
show
Supply1
=
"supply1"
...
@@ -267,7 +267,7 @@ data ChargeStrength
...
@@ -267,7 +267,7 @@ data ChargeStrength
=
Small
=
Small
|
Medium
|
Medium
|
Large
|
Large
deriving
(
Eq
,
Ord
)
deriving
Eq
instance
Show
ChargeStrength
where
instance
Show
ChargeStrength
where
show
Small
=
"small"
show
Small
=
"small"
...
...
src/Language/SystemVerilog/Parser/Tokens.hs
View file @
190c2488
...
@@ -32,14 +32,12 @@ pattern TokenEOF = Token Unknown "" (Position "" 0 0)
...
@@ -32,14 +32,12 @@ pattern TokenEOF = Token Unknown "" (Position "" 0 0)
data
Position
data
Position
=
Position
String
Int
Int
=
Position
String
Int
Int
deriving
Eq
instance
Show
Position
where
instance
Show
Position
where
show
(
Position
f
l
c
)
=
printf
"%s:%d:%d"
f
l
c
show
(
Position
f
l
c
)
=
printf
"%s:%d:%d"
f
l
c
data
Token
data
Token
=
Token
TokenName
String
Position
=
Token
TokenName
String
Position
deriving
(
Show
,
Eq
)
data
TokenName
data
TokenName
=
KW_dollar_bits
=
KW_dollar_bits
...
...
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